MC9S08QG8 Datasheet, PDF (185/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Modulo Timer (S08MTIMV1)
13.3.1 MTIM Status and Control Register (MTIMSC)
MTIMSC contains the overflow status flag and control bits, which are used to configure the interrupt enable,
reset the counter, and stop the counter.
7
6
5
4
3
R
TOF
0
0
TOIE
TSTP
W
TRST
2
1
0
0
0
0
Reset:
0
0
0
1
0
0
0
0
Figure 13-3. MTIM Status and Control Register
Table 13-2. MTIM Status and Control Register Field Descriptions
Field
Description
7
TOF
6
TOIE
5
TRST
4
TSTP
3:0
MTIM Overflow Flag — This read-only bit is set when the MTIM counter register overflows to 0x00 after reaching
the value in the MTIM modulo register. Clear TOF by reading the MTIMSC register while TOF is set, then writing
a 0 to TOF. TOF is also cleared when TRST is written to a 1 or when any value is written to the MTIMMOD register.
0 MTIM counter has not reached the overflow value in the MTIM modulo register.
1 MTIM counter has reached the overflow value in the MTIM modulo register.
MTIM Overflow Interrupt Enable — This read/write bit enables MTIM overflow interrupts. If TOIE is set, then an
interrupt is generated when TOF = 1. Reset clears TOIE. Do not set TOIE if TOF = 1. Clear TOF first, then set TOIE.
0 TOF interrupts are disabled. Use software polling.
1 TOF interrupts are enabled.
MTIM Counter Reset — When a 1 is written to this write-only bit, the MTIM counter register resets to 0x00 and
TOF is cleared. Reading this bit always returns 0.
0 No effect. MTIM counter remains at current state.
1 MTIM counter is reset to 0x00.
MTIM Counter Stop — When set, this read/write bit stops the MTIM counter at its current value. Counting resumes
from the current value when TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting.
0 MTIM counter is active.
1 MTIM counter is stopped.
Unused register bits, always read 0.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
185