MC9S08QG8 Datasheet, PDF (53/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Chapter 4 Memory Map and Register Definition
Table 4-9. Security States¹
SEC01:SEC00
Description
0:0
secure
0:1
secure
1:0
unsecured
1:1
secure
1 _{SEC01:SEC00 changes to 1:0 after successful backdoor}
key entry or a successful blank check of FLASH.
4.7.3 FLASH Configuration Register (FCNFG)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
KEYACC
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-7. FLASH Configuration Register (FCNFG)
Table 4-10. FCNFG Register Field Descriptions
Field
Description
5
KEYACC
Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed
information about the backdoor key mechanism, refer to Section 4.6, “Security.”
0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a FLASH programming or erase command.
1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes.
4.7.4 FLASH Protection Register (FPROT and NVPROT)
During reset, the contents of the nonvolatile location NVPROT is copied from FLASH into FPROT. This
register can be read at any time, but user program writes have no meaning or effect.
7
R
W
Reset
6
5
4
3
2
1
FPS⁽¹⁾
This register is loaded from nonvolatile location NVPROT during reset.
0
FPDIS⁽¹⁾
1 _{Background commands can be used to change the contents of these bits in FPROT.}
Figure 4-8. FLASH Protection Register (FPROT)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
53