MC9S08QG8 Datasheet, PDF (137/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Analog-to-Digital Converter (S08ADC10V1)
For proper conversion, the input voltage must fall between V_REFH and V_REFL. If the input is equal to or
exceeds V_REFH, the converter circuit converts the signal to $3FF (full scale 10-bit representation) or $FF
(full scale 8-bit representation). If the input is equal to or less than V_REFL, the converter circuit converts it
to $000. Input voltages between V_REFH and V_REFL are straight-line linear conversions. There will be a
brief current associated with V_REFL when the sampling capacitor is charging. The input is sampled for
3.5 cycles of the ADCK source when ADLSMP is low, or 23.5 cycles when ADLSMP is high.
For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be
transitioning during conversions.
9.6.2 Sources of Error
Several sources of error exist for A/D conversions. These are discussed in the following sections.
9.6.2.1 Sampling Error
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the
maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling
to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles @
8 MHz maximum ADCK frequency) provided the resistance of the external analog source (R_AS) is kept
below 5 kΩ.
Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the
sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.
9.6.2.2 Pin Leakage Error
Leakage on the I/O pins can cause conversion error if the external
If this error cannot be tolerated by the application, keep R_AS lower
analog source
than V_DDAD /
r(e2s_Ni*stIa_Ln_Ec_Ae_K()Rf_AorS)leissshtihgahn.
1/4LSB leakage error (N = 8 in 8-bit mode or 10 in 10-bit mode).
9.6.2.3 Noise-Induced Errors
System noise which occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are
met:
• There is a 0.1 µF low-ESR capacitor from V_REFH to V_REFL.
• There is a 0.1 µF low-ESR capacitor from V_DDAD to V_SSAD.
• If inductive isolation is used from the primary supply, an additional 1 µF capacitor is placed from
V_DDAD to V_SSAD.
• V_SSAD (and V_REFL, if connected) is connected to V_SS at a quiet point in the ground plane.
• Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or
immediately after initiating (hardware or software triggered conversions) the ADC conversion.
— For software triggered conversions, immediately follow the write to the ADCSC1 with a WAIT
instruction or STOP instruction.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
137