MC9S08QG8 Datasheet, PDF (67/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Chapter 5 Resets, Interrupts, and General System Control
5.8.3 System Background Debug Force Reset Register (SBDFR)
This high page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
7
6
5
4
3
2
1
R
0
0
0
0
0
0
0
W
Reset:
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
1 _{BDFR is writable only through serial background debug commands, not from user programs.}
Table 5-5. SBDFR Register Field Descriptions
0
0
BDFR¹
0
Field
0
BDFR
Description
Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program. To enter user mode, PTA4/ACMPO/BKGD/MS must be high immediately after
issuing WRITE_BYTE command. To enter BDM, PTA4/ACMPO/BKGD/MS must be low immediately after issuing
WRITE_BYTE command. See Table A-8., “Control Timing,” for more information.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
67