MC9S08QG8 Datasheet, PDF (147/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

10.3.3 ICS Trim Register (ICSTRM)
Internal Clock Source (S08ICSV1)
7
R
W
POR:
1
Reset:
U
6
5
4
3
TRIM
2
1
0
0
0
0
0
0
0
0
U
U
U
U
U
U
U
Figure 10-5. ICS Trim Register (ICSTRM)
Table 10-3. ICS Trim Register Field Descriptions
Field
7:0
TRIM
Description
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
10.3.4 ICS Status and Control (ICSSC)
7
R
0
W
POR:
0
Reset:
0
6
5
4
0
0
0
0
0
0
0
0
0
3
2
CLKST
0
0
0
0
1
OSCINIT
0
FTRIM
0
0
0
U
Figure 10-6. ICS Status and Control Register (ICSSC)
Table 10-4. ICS Status and Control Register Field Descriptions
Field
7:2
1
0
3:2
CLKST
Description
Reserved, should be cleared.
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is cleared only when either ERCLKEN or EREFS are cleared.
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00 Output of FLL is selected.
01 FLL Bypassed, Internal reference clock is selected.
10 FLL Bypassed, External reference clock is selected.
11 Reserved.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
147