MC9S08QG8 Datasheet, PDF (157/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Chapter 11 Inter-Integrated Circuit (S08IICV1)
Module Initialization (Slave)
1. Write: IICA
— to set the slave address
2. Write: IICC
— to enable IIC and interrupts
3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
4. Initialize RAM variables used to achieve the routine shown in Figure 11-3
Module Initialization (Master)
1. Write: IICF
— to set the IIC baud rate (example provided in this chapter)
2. Write: IICC
— to enable IIC and interrupts
3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
4. Initialize RAM variables used to achieve the routine shown in Figure 11-3
5. Write: IICC
— to enable TX
6. Write: IICC
— to enable MST (master mode)
7. Write: IICD
— with the address of the target slave. (The LSB of this byte will determine whether the communication is
master receive or transmit.)
Module Use
The routine shown in Figure 11-3 can handle both master and slave IIC operations. For slave operation, an
incoming IIC message that contains the proper address will begin IIC communication. For master operation,
communication must be initiated by writing to the IICD register.
Register Model
IICA
ADDR
0
Address to which the module will respond when addressed as a slave (in slave mode)
IICF
MULT
ICR
Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER))
IICC IICEN IICIE
MST
TX
TXAK RSTA
Module configuration
IICS TCF IAAS BUSY ARBL
0
SRW
Module status flags
IICD
DATA
Data register; Write to transmit IIC data read to read IIC data
0
IICIF
0
RXAK
Figure 11-2. IIC Module Quick Start
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
157