MC9S08QG8 Datasheet, PDF (220/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Serial Peripheral Interface (S08SPIV3)
Table 15-6. SPI Baud Rate Divisor
SPR2:SPR1:SPR0
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Rate Divisor
2
4
8
16
32
64
128
256
15.3.4 SPI Status Register (SPIS)
This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
Writes have no meaning or effect.
7
6
5
4
3
2
1
0
R SPRF
0
SPTEF
MODF
0
0
0
0
W
Reset
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-8. SPI Status Register (SPIS)
Field
7
SPRF
Table 15-7. SPIS Register Field Descriptions
Description
SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may
be read from the SPI data register (SPID). SPRF is cleared by reading SPRF while it is set, then reading the SPI
data register.
0 No data available in the receive data buffer
1 Data available in the receive data buffer
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
220
Freescale Semiconductor