MC9S08QG8 Datasheet, PDF (64/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Chapter 5 Resets, Interrupts, and General System Control
(RANGE = 0). Only the internal 1-kHz clock source can be selected to wake the MCU from stop1 or stop2
modes.
The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control
value (RTIS) used to select one of seven wakeup periods. The RTI has a local interrupt enable, RTIE, to
allow masking of the real-time interrupt. The RTI can be disabled by writing each bit of RTIS to 0s, and
no interrupts will be generated. See Section 5.8.7, “System Real-Time Interrupt Status and Control
Register (SRTISC),” for detailed information about this register.
5.8 Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to the direct-page register summary in Chapter 4, “Memory Map and Register Definition,” for the
absolute address assignments for all registers. This section refers to registers and control bits only by their
names. A Freescale-provided equate or header file is used to translate these names into the appropriate
absolute addresses.
Some control bits in the SOPT1, SOPT2, and SPMSC2 registers are related to modes of operation.
Although brief descriptions of these bits are provided here, the related functions are discussed in greater
detail in Chapter 3, “Modes of Operation.”
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
64
Freescale Semiconductor