MC9S08QG8 Datasheet, PDF (269/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Appendix A Electrical Characteristics
A.8 AC Characteristics
This section describes timing characteristics for each peripheral system.
A.8.1 Control Timing
Table A-8. Control Timing
Parameter
Symbol
Min
Typ¹
Max
Unit
Bus frequency (t_cyc = 1/f_Bus)
Real-time interrupt internal oscillator period
External reset pulse width²
IRQ pulse width
Asynchronous path²
Synchronous path³
KBIPx pulse width
Asynchronous path²
Synchronous path³
Port rise and fall time (load = 50 pF)⁴
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
f_Bus
t_RTI
t_extrst
t_ILIH
t_ILIH, t_IHIL
t_Rise, t_Fall
0
700
100
100
1.5 t_cyc
100
1.5 t_cyc
—
—
—
1000
—
—
—
3
30
10
1300
—
—
MHz
µs
ns
ns
—
ns
—
ns
—
BKGD/MS setup time after issuing background debug force
t_MSSU
500
—
reset to enter user or BDM modes
—
ns
BKGD/MS hold time after issuing background debug force
t_MSH
100
—
reset to enter user or BDM modes ⁵
—
µs
1 _{Data in Typical column was characterized at 3.0 V, 25°C.}
2 _{This is the shortest pulse that is guaranteed to be recognized.}
3 _{This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or}
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.}
5 _{To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD}
rises above V_LVD.
RESET PIN
t_extrst
Figure A-10. Reset Timing
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
269