MC9S08QG8 Datasheet, PDF (28/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Chapter 2 External Signal Description
not enabled but is configured for low output drive strength with slew rate control enabled. The PTA4 pin
defaults to BKGD/MS on any reset.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program must either enable on-chip pullup devices
or change the direction of unused pins to outputs so the pins do not float.
When using the 8-pin devices, the user must either enable on-chip pullup
devices or change the direction of non-bonded out port B pins to outputs so
the pins do not float.
2.2.5.1 Pin Control Registers
To select drive strength or enable slew rate control or pullup devices, the user writes to the appropriate pin
control register located in the high page register block of the memory map. The pin control registers
operate independently of the parallel I/O registers and allow control of a port on an individual pin basis.
2.2.5.1.1 Internal Pullup Enable
An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the
pullup enable registers (PTxPEn). The pullup device is disabled if the pin is configured as an output by the
parallel I/O control logic or any shared peripheral function, regardless of the state of the corresponding
pullup enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
The KBI module, when enabled for rising edge detection, causes an enabled internal pull device to be
configured as a pulldown.
2.2.5.2 Output Slew Rate Control
Slew rate control can be enabled for each port pin by setting the corresponding bit in one of the slew rate
control registers (PTxSEn). When enabled, slew control limits the rate at which an output can transition in
order to reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
2.2.5.3 Output Drive Strength Select
An output pin can be selected to have high output drive strength by setting the corresponding bit in one of
the drive strength select registers (PTxDSn). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this, the EMC emissions may be affected by enabling pins as high drive.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
28
Freescale Semiconductor