MC9S08QG8 Datasheet, PDF (27/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Chapter 2 External Signal Description
NOTE
In EMC-sensitive applications, an external RC filter is recommended on the
RESET pin, if enabled. See Figure 2-3 for an example.
2.2.4 Background / Mode Select (BKGD/MS)
During a power-on-reset (POR) or background debug force reset (see 5.8.3, “System Background Debug
Force Reset Register (SBDFR),” for more information), the PTA4/ACMPO/BKGD/MS pin functions as a
mode select pin. Immediately after any reset, the pin functions as the background pin and can be used for
background debug communication. When enabled as the BKGD/MS pin (BKGDPE = 1), an internal
pullup device is automatically enabled.
The background debug communication function is enabled when BKGDPE in SOPT1 is set. BKGDPE is
set following any reset of the MCU and must be cleared to use the PTA4/ACMPO/BKGD/MS pin’s
alternative pin functions.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of the
internal reset after a POR or force BDC reset. If a debug system is connected to the 6-pin standard
background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a
background debug force reset, which will force the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance
connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.2.5 General-Purpose I/O and Peripheral Ports
The MC9S08QG8/4 series of MCUs support up to 12 general-purpose I/O pins, 1 input-only pin, and 1
output-only pin, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, keyboard
interrupts, etc.). On each MC9S08QG8/4 device, there is one input-only and one output-only port pin.
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pullup device.
For information about controlling these pins as general-purpose I/O pins, see the Chapter 6, “Parallel
Input/Output Control.” For information about how and when on-chip peripheral systems use these pins,
see the appropriate chapter referenced in Table 2-2.
Immediately after reset, all pins that are not output-only are configured as high-impedance
general-purpose inputs with internal pullup devices disabled. After reset, the output-only port function is
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
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