MC9S08QG8 Datasheet, PDF (232/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Timer/PWM (S08TPMV2)
Table 16-2. TPM Clock Source Selection
CLKSB:CLKSA
TPM Clock Source to Prescaler Input
0:0
No clock selected (TPM disabled)
0:1
Bus rate clock (BUSCLK)
1:0
Fixed system clock (XCLK)
1:1
External source (TPMCLK)^1,2
1 _{The maximum frequency that is allowed as an external clock is one-fourth of the bus}
frequency.
2 _{If the external clock input is shared with channel n and is selected as the TPM clock source,}
the corresponding ELSnB:ELSnA control bits should be set to 0:0 so channel n does not try
to use the same pin for a conflicting function.
Table 16-3. Prescale Divisor Selection
PS2:PS1:PS0
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
TPM Clock Source Divided-By
1
2
4
8
16
32
64
128
16.3.2 Timer Counter Registers (TPMCNTH:TPMCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMCNTH or TPMCNTL) latches the contents of both bytes into a buffer where they
remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The coherency
mechanism is automatically restarted by an MCU reset, a write of any value to TPMCNTH or TPMCNTL,
or any write to the timer status/control register (TPMSC).
Reset clears the TPM counter registers.
7
6
5
4
3
2
R Bit 15
14
13
12
11
10
1
0
9
Bit 8
W
Any write to TPMCNTH clears the 16-bit counter.
Reset
0
0
0
0
0
0
0
0
Figure 16-4. Timer Counter Register High (TPMCNTH)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
232
Freescale Semiconductor