MC9S08QG8 Datasheet, PDF (144/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Internal Clock Source (S08ICSV1)
10.1.3.5 FLL Bypassed External (FBE)
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source. The BDC clock is supplied from the FLL.
10.1.3.6 FLL Bypassed External Low Power (FBELP)
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is
not available.
10.1.3.7 Stop (STOP)
In stop mode the FLL is disabled and the internal or external reference clocks can be selected to be enabled
or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source.
10.1.4 Block Diagram
Figure 10-2 is the ICS block diagram.
RANGE
HGO
Optional
External Reference
Clock Source
Block
EREFS
EREFSTEN
IREFSTEN
ERCLKEN
IRCLKEN
CLKS
BDIV
ICSERCLK
ICSIRCLK
Internal
Reference
LP
Clock
/ 2ⁿ
n=0-3
IREFS
/ 2ⁿ
n=0-7
9
TRIM
RDIV_CLK
DCO
9
Filter
FLL
DCOOUT
/2
RDIV
Internal Clock Source Block
Figure 10-2. Internal Clock Source (ICS) Block Diagram
ICSOUT
ICSLCLK
ICSFFCLK
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
144
Freescale Semiconductor