MC9S08QG8 Datasheet, PDF (184/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Modulo Timer (S08MTIMV1)
13.1.4 Block Diagram
The block diagram for the modulo timer module is shown Figure 13-2.
BUSCLK
XCLK
TCLK
SYNC
CLOCK
SOURCE
SELECT
PRESCALE AND
SELECT DIVIDE
BY
8-BIT COUNTER
(MTIMCNT)
TRST
TSTP
MTIM
INTERRUPT
REQUEST
CLKS
PS
8-BIT COMPARATOR
TOF
TOIE
8-BIT MODULO
(MTIMMOD)
Figure 13-2. Modulo Timer (MTIM) Block Diagram
13.2 External Signal Description
The MTIM includes one external signal, TCLK, used to input an external clock when selected as the
MTIM clock source. The signal properties of TCLK are shown in Table 13-1.
Table 13-1. Signal Properties
Signal
Function
I/O
TCLK
External clock source input into MTIM
I
The TCLK input must be synchronized by the bus clock. Also, variations in duty cycle and clock jitter must
be accommodated. Therefore, the TCLK signal must be limited to one-fourth of the bus frequency.
The TCLK pin can be muxed with a general-purpose port pin. See the Pins and Connections chapter for
the pin location and priority of this function.
13.3 Register Definition
Each MTIM includes four registers:
• An 8-bit status and control register
• An 8-bit clock configuration register
• An 8-bit counter register
• An 8-bit modulo register
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all MTIM registers. This section refers to registers and control bits only by their names
and relative address offsets.
Some MCUs may have more than one MTIM, so register names include placeholder characters to identify
which MTIM is being referenced.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
184
Freescale Semiconductor