MC9S08QG8 Datasheet, PDF (171/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Inter-Integrated Circuit (S08IICV1)
11.6.1 Byte Transfer Interrupt
The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of
byte transfer.
11.6.2 Address Detect Interrupt
When its own specific address (IIC address register) is matched with the calling address, the IAAS bit in
status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW bit
and set its Tx mode accordingly.
11.6.3 Arbitration Lost Interrupt
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters try to control the bus at the same time, the relative priority of the contending masters is determined
by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration
process and the ARBL bit in the status register is set.
Arbitration is lost in the following circumstances:
• SDA sampled as a low when the master drives a high during an address or data transmit cycle.
• SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive
cycle.
• A START cycle is attempted when the bus is busy.
• A repeated START cycle is requested in slave mode.
• A STOP condition is detected when the master did not request it.
This bit must be cleared by software by writing a one to it.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
171