MC9S08QG8 Datasheet, PDF (134/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit

Analog-to-Digital Converter (S08ADC10V1)
9.5.1 ADC Module Initialization Example
9.5.1.1 Initialization Sequence
Before the ADC module can be used to complete conversions, an initialization procedure must be carried
out, as follows:
1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio
used to generate the internal clock, ADCK. This register is also used for selecting sample time and
low-power configuration.
2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or
software) and compare function options, if enabled.
3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous
or completed only once, and to enable or disable conversion complete interrupts. The input channel
on which conversions will be performed is also selected here.
9.5.1.2 Pseudo — Code Example
In this example, the ADC module will be set up with interrupts enabled to perform a single 10-bit
conversion at low power with a long sample time on input channel 1, where the internal ADCK clock will
be derived from the bus clock divided by 1.
ADCCFG = 0x98 (%10011000)
Bit 7 ADLPC 1
Bit 6:5 ADIV
00
Bit 4 ADLSMP 1
Bit 3:2 MODE 10
Bit 1:0 ADICLK 00
Configures for low power (lowers maximum clock speed)
Sets the ADCK to the input clock ÷ 1
Configures for long sample time
Sets mode at 10-bit conversions
Selects bus clock as input clock source
ADCSC2 = 0x00 (%00000000)
Bit 7 ADACT 0
Bit 6 ADTRG 0
Bit 5 ACFE 0
Bit 4 ACFGT 0
Bit 3:2
00
Bit 1:0
00
Flag indicates if a conversion is in progress
Software trigger selected
Compare function disabled
Not used in this example
Unimplemented or reserved, always reads zero
Reserved for Freescale’s internal use; always write zero
ADCSC1 = 0x42 (%01000001)
Bit 7 COCO
Bit 6 AIEN
Bit 5 ADCO
Bit 4:0 ADCH
0
1
0
00001
Read-only flag which is set when a conversion completes
Conversion complete interrupt enabled
One conversion only (continuous conversions disabled)
Input channel 1 selected as ADC input channel
ADCRH/L = 0xxx
Holds results of conversion. Read high byte first (ADCRH) before low byte (ADCRL) so that read data
cannot be overwritten with data from the net conversion.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
134
Freescale Semiconductor