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MC9S08QG8 Datasheet, PDF (73/300 Pages) Freescale Semiconductor, Inc – 8-BIT HCS08 Central Processor Unit | |||
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Chapter 5 Resets, Interrupts, and General System Control
5.8.9 System Power Management Status and Control 2 Register
(SPMSC2)
This high page register contains status and control bits to conï¬gure the stop mode behavior of the MCU.
See Section 3.6, âStop Modes,â for more information on stop modes.
7
6
5
4
3
2
1
R
0
0
0
PDF
PPDF
0
PDC1
W
PPDACK
Reset:
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)
1 This bit can be written only one time after reset. Additional writes are ignored.
Table 5-13. SPMSC2 Register Field Descriptions
0
PPDC1
0
Field
Description
4
PDF
3
PPDF
2
PPDACK
1
PDC
0
PPDC
Power Down Flag â This read-only status bit indicates the MCU has recovered from stop1 mode.
0 MCU has not recovered from stop1 mode.
1 MCU recovered from stop1 mode.
Partial Power Down Flag â This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
Partial Power Down Acknowledge â Writing a 1 to PPDACK clears the PPDF and the PDF bits.
Power Down Control â The PDC bit controls entry into the power down (stop2 and stop1) modes
0 Power down modes are disabled.
1 Power down modes are enabled.
Partial Power Down Control â The PPDC bit controls which power down mode is selected.
0 Stop1 full power down mode enabled if PDC set.
1 Stop2 partial power down mode enabled if PDC set.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
73
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