MC908AS60ACFU Datasheet, PDF (67/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

FLASH-2 Program Operation
4. Wait for time, t_NVS.
5. Set the HVEN bit.
6. Wait for time, t_PGS.
7. Write data byte to the FLASH-2 address to be programmed.
8. Wait for time, t _PROG.
9. Repeat step 7 and 8 until all the bytes within the row are programmed.
10. Clear the PGM bit.
11. Wait for time, t_NVH.
12. Clear the HVEN bit.
13. Wait for a time, t_RCV, after which the memory can be accessed in normal read mode.
The FLASH Programming Algorithm Flowchart is shown in Figure 5-4.
NOTE
A. Programming and erasing of FLASH locations can not be performed by
code being executed from the same FLASH array.
B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address within
the FLASH array memory space such as the COP Control Register
(COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during
program/erase operations.
D. Do not exceed t _PROG maximum or t_HV maximum. t_HV is defined as the
cumulative high voltage programming time to the same row before next
erase. t_HV must satisfy this condition: t_NVS+ t_NVH + t_PGS + (t_PROGX 64) ≤ t_HV
max. Please also see 28.1.14 FLASH Memory Characteristics.
E. The time between each FLASH address change (step 7 to step 7), or the
time between the last FLASH address programmed to clearing the PGM bit
(step 7 to step 10) must not exceed the maximum programming time, t_PROG
max.
F. Be cautious when programming the FLASH-2 array to ensure that
non-FLASH locations are not used as the address that is written to when
selecting either the desired row address range in step 3 of the algorithm or
the byte to be programmed in step 7 of the algorithm. This applies
particularly to:
$0450-$047F: First row of FLASH-2 (48 bytes)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
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