MC908AS60ACFU Datasheet, PDF (329/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Interrupts
26.3.2 Voltage Conversion
When the input voltage to the ADC equals V_REFH (see 28.1.6 ADC Characteristics), the ADC converts the
signal to $FF (full scale). If the input voltage equals V_SSA, the ADC converts it to $00. Input voltages
between V_REFH and V_SSA are a straight-line linear conversion. Conversion accuracy of all other input
voltages is not guaranteed. Avoid current injection on unused ADC inputs to prevent potential conversion
error.
NOTE
Input voltage should not exceed the analog supply voltages.
26.3.3 Conversion Time
Conversion starts after a write to the ADSCR (ADC status control register, $0038), and requires between
16 and 17 ADC clock cycles to complete. Conversion time in terms of the number of bus cycles is a
function of ADICLK select, CGMXCLK frequency, bus frequency, and ADIV prescaler bits. For example,
with a CGMXCLK frequency of 4 MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz,
one conversion will take between 16 and 17 μs and there will be between 128 bus cycles between each
conversion. Sample rate is approximately 60 kHz.
Refer to 28.1.6 ADC Characteristics.
Conversion Time = ⎯¹⁶⎯^to⎯¹âŽ¯⁷ ⎯^AD⎯^C⎯^C⎯^loc⎯^k⎯^Cy⎯^cl⎯^es
ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
26.3.4 Continuous Conversion
In the continuous conversion mode, the ADC data register will be filled with new data after each
conversion. Data from the previous conversion will be overwritten whether that data has been read or not.
Conversions will continue until the ADCO bit (ADC status control register, $0038) is cleared. The COCO
bit is set after the first conversion and will stay set for the next several conversions until the next write of
the ADC status and control register or the next read of the ADC data register.
26.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes. See 28.1.6 ADC Characteristics for
accuracy information.
26.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. A CPU interrupt is generated if the COCO bit (ADC status control register, $0038) is at logic 0.
The COCO bit is not used as a conversion complete flag when interrupts are enabled.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
329