MC908AS60ACFU Datasheet, PDF (361/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

BDLC CPU Interface
27.6.4 BDLC State Vector Register
This register is provided to substantially decrease the CPU overhead associated with servicing interrupts
while under operation of a multiplex protocol. It provides an index offset that is directly related to the
BDLC’s current state, which can be used with a user-supplied jump table to rapidly enter an interrupt
service routine. This eliminates the need for the user to maintain a duplicate state machine in software.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
I3
I2
I1
I0
0
0
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R = Reserved
Figure 27-19. BDLC State Vector Register (BSVR)
I0, I1, I2, and I3 — Interrupt Source Bits
These bits indicate the source of the interrupt request that currently is pending. The encoding of these
bits are listed in Table 27-5.
Table 27-5. BDLC Interrupt Sources
BSVR I3 I2 I1 I0
$00 0 0 0 0
$04 0 0 0 1
$08 0 0 1 0
$0C 0 0 1 1
$10 0 1 0 0
$14 0 1 0 1
$18 0 1 1 0
$1C 0 1 1 1
$20 1 0 0 0
Interrupt Source
No Interrupts Pending
Received EOF
Received IFR Byte (RXIFR)
BDLC Rx Data Register Full (RDRF)
BDLC Tx Data Register Empty (TDRE)
Loss of Arbitration
Cyclical Redundancy Check (CRC) Error
Symbol Invalid or Out of Range
Wakeup
Priority
0 (Lowest)
1
2
3
4
5
6
7
8 (Highest)
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the BDLC data register needs
servicing (RDRF, RXIFR, or TDRE conditions). RXIFR and RDRF can be cleared only by a read of the
BSVR followed by a read of the BDLC data register (BDR). TDRE can either be cleared by a read of the
BSVR followed by a write to the BDLC BDR or by setting the TEOD bit in BCR2.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
361