MC908AS60ACFU Datasheet, PDF (244/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Programmable Interrupt Timer (PIT)
Register Name
Bit 7
6
5
4
3
Read: POF
0
0
POIE PSTOP
PIT Status and Control Register (PSC) Write: 0
PRST
Reset: 0
0
1
0
0
Read: Bit 15
14
13
12
11
PIT Counter Register High (PCNTH) Write:
Reset: 0
0
0
0
0
Read: Bit 7
6
5
4
3
PIT Counter Register Low (PCNTL) Write:
Reset: 0
0
0
0
0
Read:
PIT Counter Modulo Register High
(PMODH)
Write:
Bit 15
14
13
12
11
Reset: 1
1
1
1
1
Read:
PIT Counter Modulo Register Low
(PMODL)
Write:
Bit 7
6
5
4
3
Reset: 1
1
1
1
1
=Unimplemented
Figure 21-2. PIT I/O Register Summary
2
PPS2
0
10
0
2
0
10
1
2
1
1
PPS1
0
9
0
1
0
9
1
1
1
Bit 0
PPS0
0
Bit 8
0
Bit 0
0
Bit 8
1
Bit 0
1
Table 21-1. PIT I/O Register Address Summary
Register PSC PCNTH PCNTL PMODH PMODL
Address $004B $004C $004D $004E $004F
21.4 PIT Counter Prescaler
The clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates
from the internal bus clock. The prescaler select bits, PPS[2:0], in the status and control register select
the PIT clock source.
The value in the PIT counter modulo registers and the selected prescaler output determines the frequency
of the periodic interrupt. The PIT overflow flag (POF) is set when the PIT counter value reaches the
modulo value programmed in the PIT counter modulo registers. The PIT interrupt enable bit, POIE,
enables PIT overflow CPU interrupt requests. POF and POIE are in the PIT status and control register.
21.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
21.5.1 Wait Mode
The PIT remains active after the execution of a WAIT instruction. In wait mode the PIT registers are not
accessible by the CPU. Any enabled CPU interrupt request from the PIT can bring the MCU out of wait
mode.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
244
Freescale Semiconductor