MC908AS60ACFU Datasheet, PDF (290/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

MSCAN Controller (MSCAN08)
23.13.4 MSCAN08 Bus Timing Register 1
Address:
Read:
Write:
Reset:
$0503
Bit 7
6
5
4
3
2
1
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11
0
0
0
0
0
0
0
Figure 23-18. Bus Timing Register 1 (CBTR1)
Bit 0
TSEG10
0
SAMP — Sampling
This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per
bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For
higher bit rates, SAMP should be cleared, which means that only one sample will be taken per bit.
1 = Three samples per bit⁽¹⁾
0 = One sample per bit
TSEG22–TSEG10 — Time Segment
Time segments within the bit time fix the number of clock cycles per bit time and the location of the
sample point. Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in
Table 23-8.
Table 23-8. Time Segment Values
TSEG13 TSEG12 TSEG11 TSEG10
Time
Segment 1
TSEG22
0
0
0
0
1 T_q Cycle⁽¹⁾
0
0
0
0
1
2 T_q Cycles⁽¹⁾
0
0
0
1
0
3T_q Cycles⁽¹⁾
.
0
0
1
1
4 T_q Cycles
.
.
.
.
.
.
1
.
.
.
.
.
1
1
1
1
16 T_q Cycles
1. This setting is not valid. Please refer to Table 23-4 for valid settings.
TSEG21
0
0
.
.
1
TSEG20
0
1
.
.
1
Time
Segment 2
1 T_q Cycle⁽¹⁾
2 T_q Cycles
.
.
8T_q Cycles
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (T_q) clock cycles per bit as shown in Table 23-8).
Bit time=
Pres value
• number of Time Quanta
f_MSCANCLK
NOTE
The CBTR1 register can only be written if the SFTRES bit in the MSCAN08
module control register is set.
1. In this case PHASE_SEG1 must be at least 2 time quanta.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
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Freescale Semiconductor