MC908AS60ACFU Datasheet, PDF (131/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Functional Description
10.3.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See 10.5.2 PLL
Bandwidth Control Register. If PLL CPU interrupt requests are enabled, the software can wait for a PLL
CPU interrupt request and then check the LOCK bit. If CPU interrupts are disabled, software can poll the
LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK
bit is set, the VCO clock is safe to use as the source for the base clock. See 10.3.3 Base Clock Selector
Circuit. If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has
suffered a severe noise hit and the software must take appropriate action, depending on the application.
See 10.6 Interrupts.
These conditions apply when the PLL is in automatic bandwidth control mode:
• The ACQ bit (See 10.5.2 PLL Bandwidth Control Register.) is a read-only indicator of the mode of
the filter. See 10.3.2.2 Acquisition and Tracking Modes.
• The ACQ bit is set when the VCO frequency is within a certain tolerance, Δ_trk, and is cleared when
the VCO frequency is out of a certain tolerance, Δ_unt. See Chapter 28 Electrical Specifications.
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance, Δ_Lock, and is cleared
when the VCO frequency is out of a certain tolerance, Δ_unl. See Chapter 28 Electrical
Specifications.
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. See 10.5.1 PLL Control Register.
The PLL also can operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
f_busmax and require fast startup. The following conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ bit must be clear.
• Before entering tracking mode (ACQ = 1), software must wait a given time, t_acq (see Chapter 28
Electrical Specifications), after turning on the PLL by setting PLLON in the PLL control register
(PCTL).
• Software must wait a given time, t_al, after entering tracking mode before selecting the PLL as the
clock source to CGMOUT (BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
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