MC908AS60ACFU Datasheet, PDF(167/414 Page) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

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MC908AS60ACFU Datasheet, PDF (167/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

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Chapter 16

Low-Voltage Inhibit (LVI)

16.1 Introduction

This chapter describes the low-voltage inhibit module (LVI47, Version A), which monitors the voltage on

the VDD pin and can force a reset when the VDD voltage falls to the LVI trip voltage.

16.2 Features

Features of the LVI module include:

â¢ Programmable LVI Reset

â¢ Programmable Power Consumption

â¢ Digital Filtering of VDD Pin Level

NOTE

If a low voltage interrupt (LVI) occurs during programming of EEPROM or

Flash memory, then adequate programming time may not have been

allowed to ensure the integrity and retention of the data. It is the

responsibility of the user to ensure that in the event of an LVI any addresses

being programmed receive specification programming conditions.

16.3 Functional Description

Figure 16-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module

contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWR, enables the LVI to

monitor VDD voltage. The LVI reset bit, LVIRST, enables the LVI module to generate a reset when VDD

falls below a voltage, LVITRIPF, and remains at or below that level for nine or more consecutive CPU

cycles.

Note that short VDD spikes may not trip the LVI. It is the userâs responsibility to ensure a clean VDD signal

within the specified operating voltage range if normal microcontroller operation is to be guaranteed.

LVISTOP, enables the LVI module during stop mode. This will ensure when the STOP instruction is

implemented, the LVI will continue to monitor the voltage level on VDD. LVIPWR, LVISTOP, and LVIRST

are in the configuration register, CONFIG-1 (see Chapter 11 Configuration Register (CONFIG-1)).

Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, LVITRIPR. VDD must

be above LVITRIPR for only one CPU cycle to bring the MCU out of reset (see 16.3.2 Forced Reset

Operation). The output of the comparator controls the state of the LVIOUT flag in the LVI status register

(LVISR).

An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.

MC68HC908AZ60A â¢ MC68HC908AS60A â¢ MC68HC908AS60E Data Sheet, Rev. 6

Freescale Semiconductor

167

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