MC908AS60ACFU Datasheet, PDF (51/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Chapter 4
FLASH-1 Memory
4.1 Introduction
This chapter describes the operation of the embedded FLASH-1 memory. This memory can be read,
programmed and erased from a single external supply. The program and erase operations are enabled
through the use of an internal charge pump.
4.2 Functional Description
The FLASH-1 memory is an array of 32,256 bytes with two bytes of block protection (one byte for
protecting areas within FLASH-1 array and one byte for protecting areas within FLASH-2 array) and an
additional 40 bytes of user vectors on the MC68HC908AS60A and 52 bytes of user vectors on the
MC68HC908AZ60A. An erased bit reads as a logic 1 and a programmed bit reads as a logic 0.
Memory in the FLASH-1 array is organized into rows within pages. There are two rows of memory per
page with 64 bytes per row. The minimum erase block size is a single page,128 bytes. Programming is
performed on a per-row basis, 64 bytes at a time. Program and erase operations are facilitated through
control bits in the FLASH-1 Control Register (FL1CR). Details for these operations appear later in this
chapter.
The FLASH-1 memory map consists of:
• $8000–$FDFF: User Memory (32,256 bytes)
• $FF80: FLASH-1 Block Protect Register (FL1BPR)
• $FF81: FLASH-2 Block Protect Register (FL2BPR)
• $FF88: FLASH-1 Control Register (FL1CR)
• $FFCC–$FFFF: these locations are reserved for user-defined interrupt and reset vectors. (Please
see 2.4 Vector Addresses and Priority for details)
Programming tools are available from Freescale. Contact your local Freescale representative for more
information.
NOTE
A security feature prevents viewing of the FLASH contents.⁽¹⁾
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
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