MC908AS60ACFU Datasheet, PDF (362/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Byte Data Link Controller (BDLC)
Upon receiving a BDLC interrupt, the user can read the value within the BSVR, transferring it to the CPU’s
index register. The value can then be used to index into a jump table, with entries four bytes apart, to
quickly enter the appropriate service routine. For example:
Service
*
*
JMPTAB
*
LDX BSVR
JMP JMPTAB,X
JMP SERVE0
NOP
JMP SERVE1
NOP
JMP SERVE2
NOP
JMP SERVE8
END
Fetch State Vector Number
Enter service routine,
(must end in RTI)
Service condition #0
Service condition #1
Service condition #2
Service condition #8
NOTE
The NOPs are used only to align the JMPs onto 4-byte boundaries so that
the value in the BSVR can be used intact. Each of the service routines must
end with an RTI instruction to guarantee correct continued operation of the
device. Note also that the first entry can be omitted since it corresponds to
no interrupt occurring.
The service routines should clear all of the sources that are causing the pending interrupts. Note that the
clearing of a high priority interrupt may still leave a lower priority interrupt pending, in which case bits I0,
I1, and I2 of the BSVR will then reflect the source of the remaining interrupt request.
If fewer states are used or if a different software approach is taken, the jump table can be made smaller
or omitted altogether.
27.6.5 BDLC Data Register
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
D7
D6
D5
D4
D3
D2
D1
D0
Write:
Reset:
Unaffected by Reset
Figure 27-20. BDLC Data Register (BDR)
This register is used to pass the data to be transmitted to the J1850 bus from the CPU to the BDLC. It is
also used to pass data received from the J1850 bus to the CPU. Each data byte (after the first one) should
be written only after a Tx data register empty (TDRE) state is indicated in the BSVR.
Data read from this register will be the last data byte received from the J1850 bus. This received data
should only be read after an Rx data register full (RDRF) interrupt has occurred. (See 27.6.4 BDLC State
Vector Register)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
362
Freescale Semiconductor