MC908AS60ACFU Datasheet, PDF (117/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

SIM Counter
9.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources.
WARNING
Extra care should be exercised if code in this part has been migrated
from older HC08 devices since the illegal address reset specification
may be different. Also, extra care should be exercised when using this
emulation part for development of code to be run in ROM AZ, AB or
AS family parts with a smaller memory size since some legal
addresses will become illegal addresses on the smaller ROM memory
map device and may as a result generate unwanted resets.
9.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V_DD voltage falls to the V_LVII
voltage. The LVI bit in the SIM reset status register (SRSR) is set and a chip reset is asserted if the
LVIPWRD and LVIRSTD bits in the CONFIG-1 register are at logic zero. The RST pin will be held low until
the SIM counts 4096 CGMXCLK cycles after V_DD rises above V_LVIR. Another sixty-four CGMXCLK cycles
later, the CPU is released from reset to allow the reset vector sequence to occur. See Chapter 16
Low-Voltage Inhibit (LVI).
9.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the
clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of
CGMXCLK.
9.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to
drive the bus clock state machine.
9.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the CONFIG-1
register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay of 4096
CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long start-up times from stop mode. External crystal applications should use the full
stop recovery time, that is, with SSREC cleared.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
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