MC908AS60ACFU Datasheet, PDF (151/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Low-Power Modes
13.3.1 Flag Protection During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the
break state.
13.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
13.3.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
13.3.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_Hi is present on the RST pin.
13.4 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
13.4.1 Wait Mode
If enabled, the break module is active in wait mode. The SIM break wait bit (BW) in the SIM break status
register indicates whether wait was exited by a break interrupt. If so, the user can modify the return
address on the stack by subtracting one from it. (See 9.7.1 SIM Break Status Register).
13.4.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register
states.
13.5 Break Module Registers
These registers control and monitor operation of the break module:
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status and control register (BSCR)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
151