MC908AS60ACFU Datasheet, PDF (356/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Byte Data Link Controller (BDLC)
.
Table 27-3. BDLC Rate Selection
f_XCLK Frequency
R1
1.049 MHz
0
2.097 MHz
0
4.194 MHz
1
8.389 MHz
1
1.000 MHz
0
2.000 MHz
0
4.000 MHz
1
8.000 MHz
1
R0
Division
0
1
1
2
0
4
1
8
0
1
1
2
0
4
1
8
f_BDLC
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
IE— Interrupt Enable Bit
This bit determines whether the BDLC will generate CPU interrupt requests in run mode. It does not
affect CPU interrupt requests when exiting the BDLC stop or BDLC wait modes. Interrupt requests will
be maintained until all of the interrupt request sources are cleared by performing the specified actions
upon the BDLC’s registers. Interrupts that were pending at the time that this bit is cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
If the programmer does not wish to use the interrupt capability of the BDLC, the BDLC state vector
register (BSVR) can be polled periodically by the programmer to determine BDLC states. See 27.6.4
BDLC State Vector Register for a description of the BSVR.
WCM — Wait Clock Mode Bit
This bit determines the operation of the BDLC during CPU wait mode. See Stop Mode and Wait Mode
for more details on its use.
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
27.6.3 BDLC Control Register 2
This register controls transmitter operations of the BDLC. It is recommended that BSET and BCLR
instructions be used to manipulate data in this register to ensure that the register’s content does not
change inadvertently.
Address: $003D
Bit 7
6
5
4
3
2
1
Read:
Write:
Reset:
ALOOP
1
DLOOP
1
RX4XE
0
NBFS
0
TEOD
0
TSIFR
0
TMIFR1
0
Figure 27-17. BDLC Control Register 2 (BCR2)
Bit 0
TMIFR0
0
ALOOP — Analog Loopback Mode Bit
This bit determines whether the J1850 bus will be driven by the analog physical interface’s final drive
stage. The programmer can use this bit to reset the BDLC state machine to a known state after the
off-chip analog transceiver is placed in loopback mode. When the user clears ALOOP, to indicate that
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
356
Freescale Semiconductor