MC908AS60ACFU Datasheet, PDF (349/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

BDLC Protocol Handler
Since a logic 0 dominates a logic 1, the message with the lowest value will have the highest priority and
will always win arbitration. For instance, a message with priority 000 will win arbitration over a message
with priority 011.
This method of arbitration will work no matter how many bits of priority encoding are contained in the
message.
During arbitration, or even throughout the transmitting message, when an opposite bit is detected,
transmission is stopped immediately unless it occurs on the 8th bit of a byte. In this case, the BDLC
automatically will append up to two extra logic 1 bits and then stop transmitting. These two extra bits will
be arbitrated normally and thus will not interfere with another message. The second logic 1 bit will not be
sent if the first loses arbitration. If the BDLC has lost arbitration to another valid message, then the two
extra logic 1s will not corrupt the current message. However, if the BDLC has lost arbitration due to noise
on the bus, then the two extra logic 1s will ensure that the current message will be detected and ignored
as a noise-corrupted message.
27.5 BDLC Protocol Handler
The protocol handler is responsible for framing, arbitration, CRC generation/checking, and error
detection. The protocol handler conforms to SAE J1850 — Class B Data Communications Network
Interface.
NOTE
Freescale assumes that the reader is familiar with the J1850 specification
before this protocol handler description is read.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 27-12. BDLC Block Diagram
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
349