MC908AS60ACFU Datasheet, PDF (336/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Byte Data Link Controller (BDLC)
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
Addr.
$003B
$003C
$003D
$003E
$003F
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 27-1. BDLC Block Diagram
Name
Bit 7
6
5
BDLC Analog and Rou5ndtrip ^Read:
Delay Register (BARD) _Write:
ATE
RXPOL
0
R
BDLC Control Register 1 ^Read:
(BCR1) _Write:
IMSG
CLKS
R1
BDLC Control Register 2 ^Read:
(BCR2) _Write:
ALOOP
DLOOP
RX4XE
BDLC State Vector Register ^{Read: 0}
0
I3
(BSVR) _{Write: R}
R
R
Read:
BDLC Data Register (BDR)
BD7
BD6
BD5
Write:
4
0
R
R0
NBFS
I2
R
BD4
3
2
1
Bit 0
BO3
BO2
BO1
BO0
0
0
IE
WCM
R
R
TEOD TSIFR TMIFR1 TMIFR0
I1
I0
0
0
R
R
R
R
BD3
BD2
BD1
BD0
R = Reserved
Figure 27-2. BDLC I/O Register Summary
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
336
Freescale Semiconductor