MC908AS60ACFU Datasheet, PDF (360/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Byte Data Link Controller (BDLC)
If the programmer attempts to set the TMIFR1 bit immediately after the EOD symbol has been received
from the bus, the TMIFR1 bit will remain in the reset state, and no attempt will be made to transmit an
IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting any byte of a multiple byte IFR, the BDLC
will go to the loss of arbitration state, set the appropriate flag, and cease transmission.
If the BDLC loses arbitration during the IFR, the TMIFR1 bit will be cleared and no attempt will be made
to retransmit the byte in the BDR. If loss of arbitration occurs in the last two bits of the IFR byte, two
additional 1 bits will be sent out.
NOTE
The extra logic 1s are an enhancement to the J1850 protocol which forces
a byte boundary condition fault. This is helpful in preventing noise from
going onto the J1850 bus from a corrupted message.
TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 3) Bit
The TMIFR0 bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR) as
the first byte of a multiple byte IFR without CRC. Response IFR bytes are still subject to J1850
message length maximums (see J1850 Frame Format and Figure 27-18).
1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol
has been received the BDLC will attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last IFR byte has been written into
the BDR register. After TEOD has been set, the last IFR byte to be transmitted will be the last
byte which was written into the BDR register.
0 = The TMIFR0 bit will be cleared automatically; once the BDLC has successfully transmitted the
EOD symbol; by the detection of an error on the multiplex bus; or by a transmitter underrun
caused when the programmer does not write another byte to the BDR after the TDRE interrupt.
If the TMIFR0 bit is set, the BDLC will attempt to transmit the normalization symbol followed by the byte
in the BDR. After the byte in the BDR has been loaded into the transmit shift register, a TDRE interrupt
(see27.6.4 BDLC State Vector Register) will occur similar to the main message transmit sequence.
The programmer should then load the next byte of the IFR into the BDR for transmission. When the
last byte of the IFR has been loaded into the BDR, the programmer should set the TEOD bit in the
BCR2. This will instruct the BDLC to transmit an EOD symbol once the byte in the BDR is transmitted,
indicating the end of the IFR portion of the message frame. The BDLC will not append a CRC when
the TMIFR0 is set.
If the programmer attempts to set the TMIFR0 bit after the EOD symbol has been received from the
bus, the TMIFR0 bit will remain in the reset state, and no attempt will be made to transmit an IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting, the TMIFR0 bit will be cleared and no
attempt will be made to retransmit the byte in the BDR. If loss of arbitration occurs in the last two bits
of the IFR byte, two additional 1 bits (active short bits) will be sent out.
NOTE
The extra logic 1s are an enhancement to the J1850 protocol which forces
a byte boundary condition fault. This is helpful in preventing noise from
going onto the J1850 bus from a corrupted message.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
360
Freescale Semiconductor