MC908AS60ACFU Datasheet, PDF (376/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Electrical Specifications
28.1.15 BDLC Transmitter VPW Symbol Timings
Characteristic^{(1), (2) (3)}
Number Symbol
Min
Typ
Passive Logic 0
10
t_TVP1
62
64
Passive Logic 1
11
t_TVP2
126
128
Active Logic 0
12
t_TVA1
126
128
Active Logic 1
13
t_TVA2
62
64
Start-of-Frame (SOF)
14
t_TVA3
198
200
End-of-Data (EOD)
15
t_TVP3
198
200
End-of-Frame (EOF)
16
t_TV4
278
280
Inter-Frame Separator (IFS)
17
t_TV6
298
300
1. f_BDLC = 1.048576 or 1.0 MHz, V_DD = 5.0 V ± 10%, V_SS = 0 V
2. See Figure 28-3.
3. Transmit timing dependent upon BARD register matching physical transceiver timing.
Max
Unit
66
μs
130
μs
130
μs
66
μs
202
μs
202
μs
282
μs
—
μs
28.1.16 BDLC Receiver VPW Symbol Timings
Characteristic^{(1), (2), (3)}
Number Symbol
Min
Typ
Max
Passive Logic 0
10
t_TRVP1
34
64
96
Passive Logic 1
11
t_TRVP2
96
128
163
Active Logic 0
12
t_TRVA1
96
128
163
Active Logic 1
13
t_TRVA2
34
64
96
Start-of-Frame (SOF)
14
t_TRVA3
163
200
239
End-of-Data (EOD)
15
t_TRVP3
163
200
239
End-of-Frame (EOF)
16
t_TRV4
239
280
320
Break
18
t_TRV6
280
—
—
1. f_BDLC = 1.048576 or 1.0 MHz, V_DD = 5.0 V ± 10%, V_SS = 0 V
2. The receiver symbol timing boundaries are subject to an uncertainty of 1 t_BDLC μs due to sampling considerations.
3. See Figure 28-3.
Unit
μs
μs
μs
μs
μs
μs
μs
μs
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
376
Freescale Semiconductor