MC908AS60ACFU Datasheet, PDF (168/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Low-Voltage Inhibit (LVI)
V_DD
LOW V_DD
DETECTOR
LVIPWR
FROM CONFIG-1
CPU CLOCK
V_DD > LVI_TRIP = 0
V_DD < LVI_TRIP = 1
V_DD
DIGITAL FILTER
FROM CONFIG-1
LVIRST
ANLGTRIP
Stop Mode
Filter Bypass
LVIOUT
LVISTOP
FROM CONFIG-1
Figure 16-1. LVI Module Block Diagram
LVI RESET
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
$FE0F
LVI Status Register (LVISR)
Write:
= Unimplemented
Figure 16-2. LVI I/O Register Summary
16.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below the LVI_TRIPF level, software can monitor V_DD by
polling the LVIOUT bit. In the configuration register, the LVIPWR bit must be at logic 1 to enable the LVI
module, and the LVIRST bit must be at logic 0 to disable LVI resets.
16.3.2 Forced Reset Operation
In applications that require V_DD to remain above the LVI_TRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when V_DD falls to the LVI_TRIPF level and remains at or below that level for nine
or more consecutive CPU cycles. In the configuration register, the LVIPWR and LVIRST bits must be at
logic 1 to enable the LVI module and to enable LVI resets.
16.3.3 False Reset Protection
The V_DD pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI
module to reset the MCU,V_DD must remain at or below the LVI_TRIPF level for nine or more consecutive
CPU cycles. V_DD must be above LVI_TRIPR for only one CPU cycle to bring the MCU out of reset.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
168
Freescale Semiconductor