MC908AS60ACFU Datasheet, PDF (337/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Functional Description
27.3.1 BDLC Operating Modes
The BDLC has five main modes of operation which interact with the power supplies, pins, and the
remainder of the MCU as shown in Figure 27-3.
POWER OFF
V_DD ≤ V_DD (MINIMUM)
V_DD > V_DD (MINIMUM) AND
ANY MCU RESET SOURCE ASSERTED
RESET
ANY MCU RESET SOURCE ASSERTED
(FROM ANY MODE)
COP, ILLADDR, PU, RESET, LVR, POR
NO MCU RESET SOURCE ASSERTED
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
RUN
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
BDLC STOP
STOP INSTRUCTION OR
WAIT INSTRUCTION AND WCM = 1
BDLC WAIT
WAIT INSTRUCTION AND WCM = 0
Figure 27-3. BDLC Operating Modes State Diagram
27.3.1.1 Power Off Mode
This mode is entered from reset mode whenever the BDLC supply voltage, V_DD, drops below its minimum
specified value for the BDLC to guarantee operation. The BDLC will be placed in reset mode by
low-voltage reset (LVR) before being powered down. In this mode, the pin input and output specifications
are not guaranteed.
27.3.1.2 Reset Mode
This mode is entered from the power off mode whenever the BDLC supply voltage, V_DD, rises above its
minimum specified value (V_DD –10%) and some MCU reset source is asserted. The internal MCU reset
must be asserted while powering up the BDLC or an unknown state will be entered and correct operation
cannot be guaranteed. Reset mode is also entered from any other mode as soon as one of the MCU’s
possible reset sources (such as LVR, POR, COP watchdog, and reset pin, etc.) is asserted.
In reset mode, the internal BDLC voltage references are operative; V_DD is supplied to the internal circuits
which are held in their reset state; and the internal BDLC system clock is running. Registers will assume
their reset condition. Outputs are held in their programmed reset state. Therefore, inputs and network
activity are ignored.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
337