MC908AS60ACFU Datasheet, PDF (122/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

System Integration Module (SIM)
9.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while one set of peripheral clocks continue to run. Figure 9-12
shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break
wait bit, BW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the configuration
register is logic 0, then the computer operating properly module (COP) is enabled and remains active in
wait mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 9-12. Wait Mode Entry Timing
IAB
$6E0B
$6E0C $00FF $00FE $00FD $00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 9-13. Wait Recovery from Interrupt or Break
IAB
$6E0B
32
Cycles
32
Cycles
RSTVCTH RSTVCTL
IDB $A6 $A6
$A6
RST
CGMXCLK
Figure 9-14. Wait Recovery from Internal Reset
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
122
Freescale Semiconductor