MC908AS60ACFU Datasheet, PDF (289/414 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Programmer’s Model of Control Registers
23.13.3 MSCAN08 Bus Timing Register 0
Address: $0502
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Reset: 0
0
0
0
0
0
0
0
Figure 23-17. Bus Timing Register 0 (CBTR0)
SJW1 and SJW0 — Synchronization Jump Width
The synchronization jump width (SJW) defines the maximum number of time quanta (T_q) clock cycles
by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on
the bus (see Table 23-6).
Table 23-6. Synchronization Jump Width
SJW1
SJW0
Synchronization Jump Width
0
0
1 T_q cycle
0
1
2 T_q cycle
1
0
1
1
3 T_q cycle
4 T_q cycle
BRP5–BRP0 — Baud Rate Prescaler
These bits determine the time quanta (T_q) clock, which is used to build up the individual bit timing,
according to Table 23-7.
Table 23-7. Baud Rate Prescaler
BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler Value (P)
0
0
0
0
0
0
1
0
0
0
0
0
1
2
0
0
0
0
1
0
3
0
0
0
0
1
1
4
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
64
NOTE
The CBTR0 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Freescale Semiconductor
289