XRT74L74 Datasheet, PDF (8/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
RX DS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ............................................................................................ 264
RX DS3 LAPD STATUS REGISTER (ADDRESS = 0X19) ............................................................................................... 264
TABLE 56: THE RELATIONSHIP BETWEEN RXLAPDTYPE[1:0] AND THE RESULTING LAPD MESSAGE TYPE AND SIZE .............................. 265
FIGURE 93. FLOW CHART DEPICTING THE FUNCTIONALITY OF THE LAPD RECEIVER............................................................................. 266
5.3.4 THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE ..................................................................................... 267
FIGURE 94. A SIMPLE ILLUSTRATION OF THE RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK.............................................................. 267
TABLE 57: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK......... 268
FIGURE 95. ILLUSTRATION OF HOW TO INTERFACE THE TERMINAL EQUIPMENT TO THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
(FOR METHOD 1)................................................................................................................................................................. 268
TABLE 58: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXOHFRAME WAS LAST SAMPLED
"HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN ..................................................... 269
FIGURE 96. ILLUSTRATION OF THE SIGNALS THAT ARE OUTPUT VIA THE RECEIVE OVERHEAD OUTPUT INTERFACE (FOR METHOD 1). ...... 271
TABLE 59: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK (METHOD 2)
272
FIGURE 97. ILLUSTRATION OF HOW TO INTERFACE THE TERMINAL EQUIPMENT TO THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
(FOR METHOD 2)................................................................................................................................................................. 273
TABLE 60: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES ((SINCE RXOHFRAME WAS LAST SAMPLED "HIGH")
TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN.................................................................. 274
FIGURE 98. ILLUSTRATION OF THE SIGNALS THAT ARE OUTPUT VIA THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK (FOR METHOD 2).
276
5.3.5 THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE ........................................................................................ 276
FIGURE 99. A SIMPLE ILLUSTRATION OF THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK ....................................................... 277
TABLE 61: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK............. 278
FIGURE 100. ILLUSTRATION OF THE XRT74L74 DS3/E3 FRAMER IC BEING INTERFACED TO THE RECEIVE TERMINAL EQUIPMENT (SERIAL MODE
OPERATION) ....................................................................................................................................................................... 279
FIGURE 101. AN ILLUSTRATION OF THE BEHAVIOR OF THE SIGNALS BETWEEN THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK OF THE
XRT74L74 AND THE TERMINAL EQUIPMENT (SERIAL MODE OPERATION).............................................................................. 280
FIGURE 102. ILLUSTRATION OF THE XRT74L74 DS3/E3 FRAMER IC BEING INTERFACED TO THE RECEIVE SECTION OF THE TERMINAL EQUIP-
MENT (NIBBLE-MODE OPERATION) ....................................................................................................................................... 281
FIGURE 103. AN ILLUSTRATION OF THE BEHAVIOR OF THE SIGNALS BETWEEN THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK OF THE
XRT74L74 AND THE TERMINAL EQUIPMENT (NIBBLE-MODE OPERATION). ............................................................................ 282
5.3.6 RECEIVE SECTION INTERRUPT PROCESSING.................................................................................................... 282
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) .......................................................................................... 283
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)......................................................................................... 283
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)......................................................................................... 284
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ............................................................................. 284
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)......................................................................................... 285
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)......................................................................................... 285
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ............................................................................. 285
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)......................................................................................... 286
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)......................................................................................... 286
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ............................................................................. 287
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)......................................................................................... 287
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)......................................................................................... 288
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ............................................................................. 288
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)......................................................................................... 288
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)......................................................................................... 289
RXDS3 STATUS REGISTER (ADDRESS = 0X11) .......................................................................................................... 289
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)......................................................................................... 289
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)......................................................................................... 290
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)......................................................................................... 290
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)......................................................................................... 290
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)......................................................................................... 291
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)......................................................................................... 291
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ................................................................. 292
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ................................................................. 292
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ................................................................. 293
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ................................................................. 293
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ............................................................................................. 294
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ............................................................................................. 294
6.0 E3/ITU-T G.751 OPERATION OF THE XRT74L74 ............................................................................295
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 295
VI