XRT74L74 Datasheet, PDF (168/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
RxCP Configuration Register (Address = 4Ch)
BIT 7
RxLCD
RO
0
BIT 6
RDPChk
Pattern
R/W
x
BIT 5
RDPChk
Pattern
Enable
R/W
x
BIT 4
Idle Cell
Discard
R/W
x
BIT 3
BIT 2
OAM Check De-Scramble
Bit
Enable
R/W
R/W
x
x
BIT 1
RxCoset
Enable
R/W
x
BIT 0
HEC Error
Ignore
R/W
x
4.3.2.6 Data Path Integrity Check
The “Data Path Integrity” check is a test that is
continually run in order to verify that the connections
throughout the “ATM Layer” entity (e.g., from the
Receive UTOPIA Interface of the “source” UNI to the
Transmit UTOPIA Interface of the “destination” UNI)
are functioning properly.
The manner in which the “Data Path Integrity Check”
is employed is as follows. After an incoming cell has
passed through the cell delineation, HEC byte verifi-
cation, idle cell filtering and User cell filtering process,
it will be written to the RxFIFO, within the Receive
UTOPIA Interface Block. However, prior to being writ-
ten into the RxFIFO, the “Data Path Integrity Test”
pattern will be written into the 5th octet (overwriting
the HEC byte) of the “outbound” cell. This “Data Path
Integrity Test” pattern is typically of the value “55h”,
for each outbound cell. However, it can also be
configured to be an alternating pattern of “55h” and
AAh” (alternating values with each cell).
The Transmit Cell Processor, within the “destination”
UNI will perform a check of the 5th byte of all cells
that it reads from the TxFIFO; prior to computing and
overwriting this byte with the HEC byte. For more
information on how the Transmit Cell Processor
andles the “Data Path Integrity Check” test patterns,
please see section 1.2.2.6.
The Receive Cell Processor’s Handling of the
Data Path Integrity Test pattern
There are a variety of options for configuring the Re-
ceive Cell Processor to support the Data Path Integri-
ty Test. First it must be decided whether or not to trans-
mit a Data Path Integrity Test pattern, via the out-
bound cell, or just allow the outbound cell with the
HEC byte to be written to the RxFIFO. The Receive
Cell Processor can be configured by writing the ap-
propriate value into bit 5 (RDPChk Pattern Enable)
within the “RxCP Configuration Register (Address =
4Ch) as depicted below.
RxCP Configuration Register (Address = 4Ch)
Bit 7
RxLCD
RO
0
Bit 6
RDPChk
Pattern
R/W
x
Bit 5
RDPChk
Pattern Enable
R/W
x
Bit 4
Idle Cell
Discard
R/W
x
Bit 3
Bit 2
OAM Check De-Scramble
Bit
Enable
R/W
R/W
x
x
Bit 1
RxCoset
Enable
R/W
x
Bit 0
HEC Error
Ignore
R/W
x
Writing a “1” to this bit-field configures the Receive
Cell Processor to write the “Data Path Integrity Test”
pattern into the 5th octet of each “outbound” cell, prior
to transmittal to the RxFIFO. Conversely, writing a “0”
to this bit-field configures the Receive Cell Processor
to write the cell, with the HEC byte, into the RxFIFO.
Next, the Receive Cell Processor also allows for choo-
inge between two possible Data Path Integrity Test pat-
terns,by writing the appropriate value to Bit 6 (RD-
PChk Pattern) within the “RxCP Configuration” Regis-
ter (Address = 4Ch). Writing a “1” to this bit-field con-
figures the Receive Cell Processor to write a “55h”
into the 5th octet of each “outbound” cell, prior to it
being written into the RxFIFO. Conversely, writing a
“0” to this bit-field configures the Receive Cell Pro-
cessor to write an alternating pattern of “55h” or
“AAh”, into the 5th octet of each “outbound” cell, prior
to it being written into the RxFIFO. The Receive Cell
Processor will alternate between each of these two
patterns with each “outbound” cell.
Note: The contents of Bit 6 of the RxCP Configuration Reg-
ister, is ignored if Bit 5 is set to “0”.
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