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XRT74L74 Datasheet, PDF (135/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER | |||
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PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
TxPLCP G1 Byte Register (Address = 4Bh)
BIT 7
RO
BIT 6
Unused
RO
BIT 5
RO
BIT 4
BIT 3
TxPLCP FEBE Mask Yellow Alarm
R/W
R/W
BIT 2
LSS(2)
R/W
BIT 1
LSS(1)
R/W
BIT 0
LSS(0)
R/W
Writing a â1â to this bit-field will cause the Transmit
PLCP Processor to transmit G1 bytes with the FEBE
nibble value of â0hâ (independent of the number of
BIP-8 errors detected by the Receive PLCP Processor).
Writing a â0â to this bit-field will cause the Transmit
PLCP Processor to transmit G1 bytes with the correct
FEBE count, as determined by the âNear-Endâ Re-
ceive PLCP Processor.
3.3.3.6
Forcing a Yellow AlarmâVia Software
Control
The UNI allows for the generation a âYellow Alarm
(PLCP Version thereof)â via software control. In this
case, the Transmit PLCP Processor will generate a
âYellow Alarmâ by automatically setting the âRAIâ bit
within each G1 byte to â1â. This option can be exer-
cised by writing the appropriate bit to bit-field 3 of the
TxPLCP G1 Byte Register (Address = 4Bh). The bit
format of this register follows.
TxPLCP G1 Byte Register (Address = 4Bh)
BIT 7
RO
BIT 6
Unused
RO
BIT 5
RO
BIT 4
TxPLCP FEBE Mask
R/W
BIT 3
Yellow Alarm
R/W
BIT 2
LSS(2)
R/W
BIT 1
LSS(1)
R/W
BIT 0
LSS(0)
R/W
Writing a â1â to this bit-field forces the âPLCPâYellow
Alarmâ condition. Writing a â0â to this bit-field allows
the state of the RAI bit to be based upon the framing
conditions of the âNear-Endâ Receive PLCP Processor.
3.3.3.7
Transmitting Data Link Messages
via the G1 Byte
The âTxPLCP G1 Byteâ Register contains three bit-
fields that can be used to support a 24 kbps data link
between the Near-End Transmit PLCP Processor,
and the Far-End Receive PLCP Processor, as depicted
below.
TxPLCP G1 Byte Register (Address = 4Bh)
BIT 7
RO
BIT 6
Unused
RO
BIT 5
RO
BIT 4
TxPLCP FEBE Mask
R/W
BIT 3
Yellow Alarm
R/W
BIT 2
LSS(2)
R/W
BIT 1
LSS(1)
R/W
BIT 0
LSS(0)
R/W
Whatever data is written into the three bit-fields will
appear in Bits 2â0 of the incoming G1 byte at the Far-
End Receive PLCP Processor.
3.3.3.8 Inserting POH Bytes via the TxPOH
Serial Input Port
The UNI allows the users to externally insert their
own PLCP POH (Path Overhead) bytes via a serial
input interface consisting of the pins: TxPOHIns, Tx-
POH, TxPOHFrame, and TxPOHClk. This serial input
port can be activated by asserting the TxPOHIns in-
put pin (e.g., setting it âhighâ). When this pin is âlowâ,
the UNI will internally generate the POH bytes. How-
ever, when this pin is âhighâ, the users will be expect-
ed to provide their own value for the POH bytes via
the TxPOH input pin. The UNI will assert (toggle
âhighâ) the TxPOHFrame output pin when it expects
the MSB of the Z6 byte. The users will be expected to
provide their value for the Z6 byte, with the MSB first,
in descending order. Immediately after the LSB of the
Z6 byte, the TxPOH Serial Input port will be expecting
the MSB of the Z5 byte, and so on. The byte order
that this serial input port expects is as presented in
Table 16 . Once the TxPOH serial input port has read
in the LSB of the C1 byte, it will repeat this sequence
of bytes, beginning with the Z6 byte first. The POH
data will be serially latched into the TxPOH input on
the rising edge of the TxPOHClk output signal. The
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