XRT74L74 Datasheet, PDF (111/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
Receive UTOPIA Interface blocks, within UNIs #1 and
#2 is presented in Section 7.4.2.2.2.2.1.
Polling Operation
Consider that the ATM Layer processor is currently
writing a continuous stream of ATM cell data into UNI
#1. While writing this cell data into UNI #1, the ATM
Layer processor can also “poll” UNI #2 for “availability”
(e.g., tries to determine if the ATM Layer processor
can write any more ATM cell data into the “Transmit
UTOPIA Interface block” within UNI #2).
The ATM Layer Processor’s Role in the “Polling”
Operation
The ATM Layer processor accomplishes this “polling”
operation by executing the following steps.
1. Assert the TxUEn input pin (if it is not asserted
already).
The UNI device (being “polled”) will know that this is
only a “polling” operation, if the TxUEn input pin is as-
serted, prior to detecting its UTOPIA Address on the
“UTOPIA Address” bus.
2. The ATM Layer processor places the address of
the Transmit UTOPIA Interface Block of UNI #2
onto the UTOPIA Address Bus, Ut_Addr[4:0],
3. The ATM Layer processor will then check the
value of its “TxUClav_in” input pin (see Figure 9 ).
The UNI Devices Role in the “Polling” Operation
UNI #2 will sample the signal levels placed on its Tx-
UTOPIA Address input pins (TxUAddr[4:0]) on the ris-
ing edge of its “Transmit UTOPIA Interface block”
clock input signal, TxUClk. Afterwards, UNI #2 will
compare the value of these “Transmit UTOPIA Ad-
dress Bus input pin” signals with that of the contents
of its “TxUTOPIA Address Register (Address = 70h).
If these values do not match, (e.g., TxUAddr[4:0]
¦02h) then UNI #2 will keep its “TxUClav” output sig-
nal “tri-stated”; and will continue to sample its “Trans-
mit UTOPIA Address bus input” pins; with each rising
edge of TxUClk.
If these two values do match, (e.g., TxUAddr[4:0] =
02h) then UNI #2 will drive its “TxUClav” output pin to
the appropriate level, reflecting its TxFIFO “fill-status”.
Since the UNI is automatically operating in the “Cell
Level Handshaking” mode while it is operating in the
“Multi-PHY” mode; the UNI will drive the TxUClav out-
put signal “high” if it is capable of receiving at least
one more complete cell of data from the ATM Layer
processor. Conversely, the UNI will drive the “TxU-
Clav” output signal “low” if its TxFIFO is too full and is
incapable of receiving one more complete cell of data
from the ATM Layer processor.
When UNI #2 has been selected for “polling”, UNI #1
will continue to keeps its “TxUClav” output signal “tri-
stated”. Therefore, when UNI #2 is driving its “TxU-
Clav” output pin to the appropriate level, it will be driv-
ing the entire “TxUClav” line, within the “Multi-PHY”
system. Consequently, UNI#2 will also be driving the
“TxUClav_in” input pin of the ATM Layer processor
(see Figure 11 ).
If UNI #2 drives the “TxUClav” line “low”, upon the ap-
plication of its address on the UTOPIA Address Bus,
then the ATM Layer processor will “learn” that it cannot
write any more cell data to this UNI device; and will
deem this device “unavailable”. However, if UNI #2
drives the TxUClav line “high” (during “polling”), then
the ATM Layer processor will know that it can write cell
data into the Transmit UTOPIA Interface block, of UNI
# 2.
Figure 12 presents a timing diagram that depicts the
behavior of the ATM Layer processor’s and the UNI’s
signals during polling.
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