XRT74L74 Datasheet, PDF (489/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
COFA
Interrupt
Enable
R/W
X
BIT 3
OOF
Interrupt
Enable
R/W
0
BIT 2
LOF
Interrupt
Enable
R/W
0
BIT 1
LOS
Interrupt
Enable
R/W
0
BIT 0
AIS
Interrupt
Enable
R/W
0
Writing a “1” into this bit-field enables the Change of
Framing Alignment Interrupt. Conversely, writing a
“0” into this bit-field disables the Change of Framing
Alignment Interrupt.
Servicing the Change of Framing Alignment Interrupt
Whenever the XRT74L74 Framer IC generates this
interrupt, it will do the following.
• It will assert the Interrupt Request output pin (INT)
by driving it “Low”.
• It will set Bit 4 (COFA Interrupt Status), within the
Rx E3 Interrupt Status Register -2, to “1”, as indi-
cated below.
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
COFA
Interrupt
Status
RUR
1
BIT 3
OOF
Interrupt
Status
RUR
0
BIT 2
LOF
Interrupt
Status
RUR
0
BIT 1
LOS
Interrupt
Status
RUR
0
BIT 0
AIS
Interrupt
Status
RUR
0
7.3.6.2.5 The Change in Receive AIS Condition
Interrupt
If the Change in Receive AIS Condition Interrupt is
enabled, then the XRT74L74 Framer IC will generate
an interrupt in response to either of the following con-
ditions.
1. When the XRT74L74 Framer IC declares an AIS
(Loss of Signal) Condition, and
2. When the XRT74L74 Framer IC clears the AIS
condition.
Conditions causing the XRT74L74 Framer IC to
declare an AIS Condition.
• If the XRT74L74 Framer IC detects 7 or less “0”
within 2 consecutive E3 frames.
Conditions causing the XRT74L74 Framer IC to
clear the AIS Condition.
• If the XRT74L74 Framer IC detects 2 consecutive
E3 frames that each contain 8 or more “0’s”.
Enabling and Disabling the Change in Receive
AIS Condition Interrupt
The user can enable or disable the Change in Re-
ceive LOS Condition Interrupt, by writing the appro-
priate value into Bit 0 (AIS Interrupt Enable), within
the RxE3 Interrupt Enable Register - 1, as indicated
below.
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
COFA
Interrupt
Enable
R/W
0
BIT 3
OOF
Interrupt
Enable
R/W
0
BIT 2
LOF
Interrupt
Enable
R/W
0
BIT 1
LOS
Interrupt
Enable
R/W
X
BIT 0
AIS
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con- rupt.
versely, setting this bit-field to “0” disables this inter-
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