XRT74L74 Datasheet, PDF (124/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
TABLE 10: BIT FORMAT OF THE TXCP IDLE CELL PATTERN -HEADER BYTES AND TXCP CELL PAYLOAD REGISTERS
REGISTER
TxCP Idle Cell Pattern—Header Byte 1
TxCP Idle Cell Pattern—Header Byte 2
TxCP Idle Cell Pattern—Header Byte 3
TxCP Idle Cell Pattern—Header Byte 4
TxCP Idle Cell Pattern—Header Byte 5
TxCP Idle Cell Payload
BIT 7
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
Transmit Idle Cell Pattern—Header Byte 1
Transmit Idle Cell Pattern—Header Byte 2
Transmit Idle Cell Pattern—Header Byte 3
Transmit Idle Cell Pattern—Header Byte 4
Transmit Idle Cell Pattern—Header Byte 5
Transmit Idle Cell Payload
BIT 0
TABLE 11: ADDRESS AND DEFAULT VALUES OF THE TXCP IDLE CELL PATTERN REGISTERS
ADDRESS
64h
65h
66h
67h
68h
69h
REGISTER
TxCP Idle Cell Pattern—Header Byte 1
TxCP Idle Cell Pattern—Header Byte 2
TxCP Idle Cell Pattern—Header Byte 3
TxCP Idle Cell Pattern—Header Byte 4
TxCP Idle Cell Pattern—Header Byte 5
TxCP Idle Cell Payload
DEFAULT VALUE
00h
00h
00h
01h
52h
5Ah
The role of the registers for Idle Cell Pattern—Bytes 1
through 4 is quite straightforward. When the Transmit
Cell Processor opts to generate an Idle cell, it will
read in the content of these registers and send these
values onto the HEC Byte Calculator. Consequently,
the contents of the “Transmit Idle Cell Pattern—Head-
er Byte 5” will likely be overwritten by the HEC Byte
Calculator in the Idle Cell, unless the HEC Byte Cal-
culator has been disabled (See Section 6.2.2.1.2). The
payload portion of these Idle Cells is defined by the
contents of the Transmit Idle Cell Payload Register
(Address = 69h), repeated 48 times. When the Transmit
Cell Processor reads in this register to form the cell
payload, the resulting payload will be sent on to the
Cell Scrambler and is (optionally) scrambled just like
any assigned cell.
The UNI will keep track of the number of Idle cells that
have been generated and transmitted to the Transmit
PLCP Processor (or the Transmit DS3 Framer). The
Transmit Cell Processor increments the contents of
the “PMON Transmitted Idle Cell Count (MSB and
LSB)” Registers (Address = 38h and 39h) for each
Idle Cell that is generated and transmitted. These two
registers are “Reset-upon-Read” registers that, when
concatenated, presents a 16-bit representation of the
total number of idle cells generated and transmitted
since the last time these registers were read. The bit
format of these two registers follow.
PMON Transmitted Idle Cell Count—MSB (Address = 38h)
BIT 7
RO
0
BIT 6
RO
0
BIT 5
RO
0
BIT 4
BIT 3
Tx Idle Cell Count—High Byte
RO
RO
0
0
BIT 2
RO
0
BIT 1
RO
0
BIT 0
RO
0
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