XRT74L74 Datasheet, PDF (14/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
BY THE TRANSMIT E3 LIU INTERFACE BLOCK....................................................................................................................... 436
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................................. 436
TABLE 98: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE TXLINECLK
CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ................................................................................................... 436
FIGURE 190. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG ARE CONFIGURED TO BE
UPDATED ON THE RISING EDGE OF TXLINECLK ..................................................................................................................... 437
FIGURE 191. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG ARE CONFIGURED TO BE
UPDATED ON THE FALLING EDGE OF TXLINECLK ................................................................................................................... 437
7.2.6 TRANSMIT SECTION INTERRUPT PROCESSING ................................................................................................. 437
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) .......................................................................................... 438
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) .......................................................................... 438
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) .......................................................................... 439
7.3 THE RECEIVE SECTION OF THE XRT74L74 (E3 MODE OPERATION) ................................................... 439
FIGURE 192. THE RECEIVE SECTION OF THE XRT74L74 WHEN IT HAS BEEN CONFIGURED TO OPERATE IN THE E3 MODE ..................... 439
7.3.1 THE RECEIVE E3 LIU INTERFACE BLOCK ........................................................................................................... 439
FIGURE 193. THE RECEIVE E3 LIU INTERFACE BLOCK ........................................................................................................................ 440
FIGURE 194. BEHAVIOR OF THE RXPOS, RXNEG AND RXLINECLK SIGNALS DURING DATA RECEPTION OF UNIPOLAR DATA .................. 440
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................................. 441
TABLE 99: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE TXLINECLK
CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ................................................................................................... 441
FIGURE 195. ILLUSTRATION ON HOW THE XRT74L74 RECEIVE E3 FRAMER IS INTERFACED TO THE XRT73L00 LINE INTERFACE UNIT WHILE
OPERATING IN THE BIPOLAR MODE (ONE CHANNEL SHOWN)................................................................................................... 442
FIGURE 196. AMI LINE CODE ............................................................................................................................................................. 443
FIGURE 197. TWO EXAMPLES OF HDB3 DECODING............................................................................................................................. 443
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................................. 444
TABLE 100: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER, AND THE SAMPLING EDGE
OF THE RXLINECLK SIGNAL ................................................................................................................................................. 444
FIGURE 198. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND RXNEG ARE TO BE SAM-
PLED ON THE RISING EDGE OF RXLINECLK ........................................................................................................................... 445
FIGURE 199. WAVEFORM/TIMING RELATIONSHIP BETWEEN RXLINECLK, RXPOS AND RXNEG - WHEN RXPOS AND RXNEG ARE TO BE SAM-
PLED ON THE FALLING EDGE OF RXLINECLK ......................................................................................................................... 445
7.3.2 THE RECEIVE E3 FRAMER BLOCK ....................................................................................................................... 445
FIGURE 200. THE RECEIVE E3 FRAMER BLOCK AND THE ASSOCIATED PATHS TO THE OTHER FUNCTIONAL BLOCKS ............................. 446
FIGURE 201. THE STATE MACHINE DIAGRAM FOR THE RECEIVE E3 FRAMER E3 FRAME ACQUISITION/MAINTENANCE ALGORITHM ......... 447
FIGURE 202. THE E3, ITU-T G.832 FRAMING FORMAT ....................................................................................................................... 448
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ...................................................................................... 449
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)............................................................................. 449
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ...................................................................................... 450
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ...................................................................................... 450
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)............................................................................. 450
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52)........................................................ 451
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53)......................................................... 451
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)............................................................................. 451
TABLE 101: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE FRAMING STATE OF THE
RECEIVE E3 FRAMER BLOCK ............................................................................................................................................... 452
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)............................................................................. 452
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ...................................................................................... 452
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)............................................................................. 453
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ...................................................................................... 453
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)............................................................................. 453
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)............................................................................. 454
THE MAINTENANCE AND ADAPTATION (MA) BYTE FORMAT............................................................................................ 454
RXE3 CONFIGURATION & STATUS REGISTER 1 - (E3, ITU-T G.832) (ADDRESS = 0X10)............................................. 454
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) ...................................................................................... 455
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)............................................................................. 455
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11)............................................................................. 455
FIGURE 203. THE LOCAL RECEIVE E3 FRAMER BLOCK, RECEIVING AN E3 FRAME FROM THE REMOTE TERMINAL WITH A CORRECT EM BYTE.
456
FIGURE 204. THE LOCAL RECEIVE E3 FRAMER BLOCK, TRANSMITTING AN E3 FRAME TO THE REMOTE TERMINAL WITH THE FEBE BIT WITHIN
THE MA BYTE-FIELD SET TO “0” ........................................................................................................................................... 456
FIGURE 205. THE LOCAL RECEIVE E3 FRAMER BLOCK, RECEIVING AN E3 FRAME FROM THE REMOTE TERMINAL WITH AN INCORRECT EM BYTE.
457
FIGURE 206. THE LOCAL RECEIVE E3 FRAMER BLOCK, TRANSMITTING AN E3 FRAME TO THE REMOTE TERMINAL WITH THE FEBE BIT WITHIN
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