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XRT74L74 Datasheet, PDF (158/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER | |||
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XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
RxCP Configuration Register (Address = 4Ch)
BIT 7
RxLCD
RO
0
BIT 6
RDPChk
Pattern
R/W
x
BIT 5
RDPChk
Pattern Enable
R/W
x
BIT 4
Idle Cell
Discard
R/W
x
BIT 3
OAM Check
Bit
R/W
x
BIT 2
De-Scramble
Enable
R/W
x
BIT 1
RxCoset
Enable
R/W
x
BIT 0
HEC Error
Ignore
R/W
x
If a â0â is written to this bit-field, then the Idle Cells will
be retained and will ultimately be sent on to the User
Cell Filter within the Receive Cell Processor block.
However, if a â1â is written to this bit-field, then the Re-
ceive Cell Processor will discard all detected Idle-cells.
If the user wishes to have the Receive Cell Processor
discard the Idle Cells, the header byte patterns of
these Idle cells must be specified. The Idle Cell head-
er byte pattern is defined based upon the content of 8
read/write registers. These eight registers are the four
âRxCP Idle Cell Pattern Header byte registers, and the
four âRxCP Idle Cell Mask HeaderâByteâ Registers.
In short, when a cell reaches the âIdle Cell Filterâ por-
tion of the Receive Cell Processor, the contents of
each header byte of this cell (bytes 1 through 4), will
be compared against the contents of the correspond-
ing âRxCP Idle Cell Pattern Header Byteâ registers,
based upon constraints specified by the contents
within the âRxCP Idle Cell Mask Header Byteâ regis-
ters. The use of these registers in âIdle Cell Identifica-
tionâ and filtering is illustrated in the example below.
ExampleâIdle Cell Filtering
For example, header byte 1 of a given incoming cell
(which may be an Idle cell or a User cell) will be sub-
jected to a bit-by-bit comparison to the contents of the
âRxCP Idle Cell Pattern Header Byte-1â register (Ad-
dress = 50h). The purpose of having the Receive Cell
Processor perform this comparison is to determine if
this incoming cell is an Idle Cell or not. The contents
of the âRxCP Idle Cell Mask Header Byte-1â register
(Address = 54h) also plays a role in this comparison
process. For instance, if bit-field â0â within the âRxCP
Idle Cell Mask Header Byte-1â register contains a â1â,
then the Receive Cell Processor will perform the com-
parison operation between bit-field â0â within the âRx-
CP Idle Cell Pattern Header Byte-1â register; and bit-
field â0â within header byte 1 of the newly received
cell. Conversely, if bit-field â0â within the âRxCP Idle
Cell Mask Header Byte-1â register contains a â0â,
then this comparison will not be made and bit-field â0â
will be treated as a âdonât careâ. The role of these two
read/write registers, in these comparison operations is
more clearly defined in Table 25 , below.
TABLE 25: ILLUSTRATION OF THE ROLE OF THE âRXCP IDLE CELL PATTERN HEADER BYTEâ REGISTER, AND THE
âRXCP IDLE CELL MASK HEADER BYTEâ REGISTER
Content of Header Byte-1 (of Incoming Cell)
BIT 7
BIT 6
BIT 5
BIT 4
1
0
1
0
BIT 3
0
BIT 2
1
BIT 1
0
BIT 0
1
Content of âRxCP Idle Cell Mask Header Byte-1 Register
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
1
1
1
1
0
Content of âRxCP Idle Cell Header Byte-1 Register
BIT 7
BIT 6
BIT 5
BIT 4
1
0
1
0
BIT 3
1
BIT 2
0
BIT 2
1
BIT 1
0
BIT 1
0
BIT 0
0
BIT 0
1
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