XRT74L74 Datasheet, PDF (102/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
FIGURE 5. TIMING DIAGRAM OF TXUCLAV/TXFULLB AND VARIOUS OTHER SIGNALS DURING WRITES TO THE TRANSMIT
UTOPIA, WHILE OPERATING IN THE OCTET-LEVEL HANDSHAKING MODE.
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2
3
4
5
6
7
8
9
10
11
12
TxUClk
TxUClav
TxUEn
TxUData [15:0] _W20 W21 W22 W23 W24 W25
X
X
X
W26 W0 W1
TxUSoC
Note: regarding Figure 5
1. The Transmit UTOPIA Data Bus is configured to
be 16 bits wide. Hence, the data which the ATM
Layer processor places on the Transmit UTOPIA
Data Bus is expressed in terms of 16-bit words:
(e.g., W0–W26).
2. The Transmit UTOPIA Interface block is config-
ured to handle 54 bytes/cell. Hence, Figure 5
illustrates the ATM Layer processor writing 27
words (W0 through W26) for each ATM cell.
In Figure 5 , TxUClav is initially “high” during clock
edge # 1. However, shortly after the ATM Layer pro-
cessor writes in word W20, TxUClav toggles “low”,
indicating that the TxFIFO is starting to fill up. The
ATM Layer processor will detect this “negation of
TxUClav” during clock edge #2; while it is writing
word W21 into the Transmit UTOPIA Interface block.
At this point, the ATM Layer processor is only permit-
ted to execute four more “write” operations with the
Transmit UTOPIA Interface block. Therefore, the ATM
Layer processor will proceed to write in words: W22,
W23, W24 and W25 before negating TxUEn. The
ATM Layer processor must keep TxUEn negated until
it detects that TxUClav has once again returned
“high”. In Figure 5 , TxUClav is asserted after clock
edge #8. The ATM Layer processor detects this tran-
sition in TxUClav at clock edge #9; and subsequently,
asserts TxUEn. The ATM Layer resumes writing in
more ATM cell data into the Transmit UTOPIA
Interface block.
3.1.2.3.0.2 Cell-Level Handshaking
The UNI will be operating in the “Cell-Level” Hand-
shaking mode following power up or reset. In the
“Cell-Level” Handshaking mode, when the TxUClav is
at a logic “1”, it means that the TxFIFO has enough
remaining empty space for it to receive at least one
more full cell of data from the ATM Layer processor.
However, when TxUClav toggles from “high” to “low”,
it indicates that the very next cell (following the one
that is currently being written) cannot be accepted by
the TxFIFO. Conversely, once TxUClav has returned
to the logic “1” level, it indicates that at least one more
full cell may be written into the TxFIFO by the ATM
Layer processor. As in the “Octet-Level” Handshake
mode, the ATM Layer processor is expected to poll
the TxUClav output towards the end of transmission
of the cell currently being written and to proceed with
transmission of the next cell only if TxUClav is at a
logic “high”.
The UNI can operate in either the “Octet-Level” or the
“Cell-Level” Handshake mode, when operating in the
Single-PHY mode. However, only the “Cell-Level”
Handshake Mode is available when the UNI is operat-
ing in the Multi-PHY mode. For more information on
Single PHY and Multi PHY operation, please see
Section 6.1.2.3.
The UNI can be configured to operate in one of these
two handshake modes by writing the appropriate data
to Bit 5 (Handshake Mode) within the UTOPIA Con-
figuration Register, as depicted below.
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