XRT74L74 Datasheet, PDF (186/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
Figure 44 presents a timing diagram, that depicts the
behavior of the ATM Layer processor’s and the UNI’s
signals during polling.
FIGURE 44. TIMING DIAGRAM ILLUSTRATING THE BEHAVIOR OF VARIOUS SIGNALS FROM THE ATM LAYER PROCESSOR
AND THE UNI, DURING POLLING.
1
2
3
4
5
6
7
8
9
10
11
12
RxUClk
RxUAddr[4:0] 01h 1Fh
RxUClav
01h
RxUEn
RxUData [15:0] W27 W0
RxUSoC
03h 1Fh
03h
01h 03h 1Fh
01h _03h
03h 01h 1Fh
03h
01h
01h 03h
01h
W1
W2 W3
W4
W5
W6 W7
W8
W9 W10
Note: regarding Figure 44
1. The Receive UTOPIA Data bus is configured to be
16 bits wide. Hence, the data, which the ATM Layer
processor places on the Receive UTOPIA Data
bus, is expressed in terms of 16 bit words: (e.g.,
W0–W26).
2. The Receive UTOPIA Interface block is configured
to handle 54 bytes/cell. Hence, Figure 44 illus-
trates the ATM Layer processor reading 27 words
(W0 through W26) for each ATM cell.
3. The ATM Layer processor is currently reading ATM
cell data from the Receive UTOPIA Interface block,
within UNI #1 (RxUAddr[4:0] = 01h) during this “poll-
ing process”.
4. The RxFIFO, within UNI#2’s Receive UTOPIA Inter-
face block (RxUAddr[4:0] = 03h) is either depleted
or does not contain enough data to constitute a
complete ATM cell. Hence, the RxUClav line will be
driven “low” whenever this particular Receive UTO-
PIA Interface block is “polled”.
5. The Receive UTOPIA Address of 1Fh is not associ-
ated with any UNI device, within this “Multi-PHY”
system. Hence, the RxUClav line is tri-stated when-
ever this address is “polled”.
Note: Although Figure 44 depicts connections between the
Transmit UTOPIA Interface block pins and the ATM Layer
processor; the Transmit UTOPIA Interface operation, in the
Multi-PHY mode, will not be discussed in this section. Please
see Section 6.1.2.3.2.1 for a discussion on the Transmit
UTOPIA Interface block during Multi-PHY operation.
4.4.2.2.3.1.2 Reading ATM Cell Data from
a Different UNI
After the ATM Layer processor has “polled” each of
the UNI devices within its system, it must now select
a UNI, and begin reading ATM cell data from that
device. The ATM Layer processor makes its selection
and begins the reading process by:
1. Applying the UTOPIA Address of the “target” UNI
on the “UTOPIA Address Bus”.
2. Negate the RxUEn signal. This step causes the
“addressed” UNI to recognize that it has been
selected to transmit the next set of ATM cell data
to the ATM Layer processor.
3. Assert the RxUEn signal.
4. Check and insure that the RxUSoC output pin (of
the selected UNI) pulses “high” when the first
byte or word of ATM cell data has been placed on
the Receive UTOPIA Data Bus.
5. Begin reading the ATM Cell data in a byte-wide
(or word-wide) manner from the Receive UTOPIA
Data bus.
Figure 45 presents a flow-chart that depicts the “UNI
Device Selection and Read” process in Multi-PHY
operation.
184