XRT74L74 Datasheet, PDF (176/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
PRELIMINARY
FIGURE 37. TIMING DIAGRAM OF RXUCLAV/RXEMPTYB AND VARIOUS OTHER SIGNALS DURING READS FROM THE
RECEIVE UTOPIA, WHILE OPERATING IN THE OCTET-LEVEL HANDSHAKING MODE.
1
2
3
4
5
6
7
8
9
10
11
12
RxUClk
RxUClav
RxUEn
RxUData [15:0]
W0 W1
X
W2 W3
W4
RxUSoC
Note: regarding Figure 37
1. The Receive UTOPIA Data bus is configured to be
16 bits wide. Hence, the data which the Receive
UTOPIA Interface block places on the Receive
UTOPIA Data bus is expressed in terms of 16 bit
words (e.g., W0–W26).
2. The Receive UTOPIA Interface block is configured
to handle 54 bytes/cell. Hence, Figure 37 illus-
trates the ATM Layer processor reading 27 words
(W0 through W26) for each ATM cell.
In Figure 37 , RxUClav is initially “low” during clock
edge #1. However, shortly after clock edge 1, the
RxFIFO receives ATM cell data from the Receive Cell
Processor block. At this point, the RxUClav signal tog-
gles “high” indicating that the RxFIFO contains at
least one “read-cycle” worth of cell data. The ATM
Layer processor will detect this “assertion of RxU-
Clav” during clock edge #2. Consequently, in order to
begin reading this cell data, the ATM Layer processor
will then assert the RxUEn input pin. At clock edge
#3, the Receive UTOPIA Interface block detects
RxUEn being “low”. Hence, the Receive UTOPIA
Interface block then places word W0 on the Receive
UTOPIA Data bus. The ATM Layer processor latches
and reads in W0, upon clock edge #4. In this figure,
shortly after the ATM Layer processor has read in
word W1 (at clock edge #5), the RxFIFO is depleted
which causes RxUClav to toggle “low”. In this figure,
the ATM Layer processor will keep the RxUEn signal
asserted, and will read in an “invalid” word which is
denoted by the “X” in Figure 37 . Shortly thereafter,
the RxFIFO receives some additional cell data from
the Receive Cell Processor, which in turn causes
RxUClav to toggle “high”. The ATM Layer processor
then continues to read in words W2 and W3. After-
wards, the ATM Layer processor is unable to continue
reading the ATM cell data from the Receive UTOPIA
Interface block; and subsequently negates the RxUEn
signal; at clock edge #8. The Receive UTOPIA Inter-
face block detects that RxUEn is “high” at clock edge
#8, and in turn, tri-states the Receive UTOPIA Data
Bus at around clock edge # 9. Finally, prior to clock
edge #11, the ATM Layer processor is able to resume
reading in ATM cell data from the Receive UTOPIA
Interface block, and indicates this fact by asserting
the RxUEn (e.g., toggling it “low”). The Receive UTO-
PIA Interface block detects this state change at clock
edge #11 and subsequently places word W4 on the
Receive UTOPIA Data bus.
4.4.2.2.1.2 Cell Level Handshaking
The UNI will be operating in the “Cell-Level” Hand-
shaking mode following power up or reset. In the
“Cell-Level” Handshaking mode, when the RxUClav
output is at a logic “1”, it means that the RxFIFO con-
tains at least one complete ATM cell of data that is
available for reading by the ATM Layer Processor.
When RxUClav toggles from “high” to “low”, it indi-
cates that RxFIFO contains less than one complete
ATM cell. As in the “Octet-Level” Handshake mode, the
ATM Layer processor is expected to monitor the RxU-
Clav output, and quickly respond and read the
RxFIFO, whenever the RxUClav output signal is as-
serted.
The UNI can operate in either the “Octet-Level” or
“Cell-Level” Handshake mode, when operating in the
Single-PHY mode. However, only the Cell-Level
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