XRT74L74 Datasheet, PDF (105/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
Status Register (Address = 71h). The bit format of this
register is presented below.
Transmit UTOPIA FIFO Status Register (Address = 71h)
BIT 7
RO
BIT 6
RO
BIT 5
BIT 4
Unused
RO
RO
BIT 3
RO
BIT 2
RO
BIT 1
TxFIFO Full
RO
BIT 0
TxFIFO Empty
RO
The following tables define the values for Bits 1 and 0
and the corresponding meaning.
TxFIFO Full
TXFIFO FULL (BIT 1)
0
1
MEANING
TxFIFO is full, the ATM Layer processor risks causing an overrun if it writes to the TxFIFO now.
TxFIFO is not full.
TxFIFO Empty
TXFIFO EMPTY (BIT 0)
MEANING
0
TxFIFO is not empty
1
TxFIFO is empty. The TxCell Processor is currently generating IDLE cells
3.1.2.4 UTOPIA Modes of Operation (Single
PHY and Multi-PHY operation)
The UNI chip can support both Single-PHY and Multi-
PHY operation. Each of these operating modes are
discussed below.
3.1.2.4.1 Single PHY Operation
The UNI chip will be operating in the Multi-PHY mode
upon power up or reset. Therefore, a “1” must be writ-
ten to Bit 4 within the UTOPIA Configuration register
(Address = 6Ah) in order to configure the UNI into the
Single-PHY Mode.
UTOPIA Configuration Register: Address = 6Ah
BIT 7
BIT 6
Unused
RO
BIT 5
BIT 4
BIT 3
Handshake Mode S-PHY/M-PHY* CellOf52 Bytes
R/W
R/W
R/W
BIT 2
BIT 1
TFIFODepth[1, 0]
R/W
BIT 0
UtWidth16
R/W
Writing a ‘1’ to this bit-field configures the UNI to op-
erate in the Single-PHY Mode. Writing a ‘0’ config-
ures the UNI to operate in the Multi-PHY Mode.
In Single-PHY operation, the ATM layer processor is
pumping data into and receiving data from only one
UNI device, as depicted in Figure 7 .
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