XRT74L74 Datasheet, PDF (3/498 Pages) Exar Corporation – 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER

PRELIMINARY
XRT74L74
4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.1.1
TABLE OF CONTENTS
GENERAL DESCRIPTION.............................................................................................................. 1
FEATURES..................................................................................................................................................................... 1
APPLICATIONS ............................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XRT74L74 ATM UNI/PPP DS3/E3 FRAMING CONTROLLER............................................................. 1
FIGURE 2. PIN OUT OF THE XRT74L74 DS3/E3 ATM UNI/PPP (388 BALL PBGA)............................................................................... 2
ORDERING INFORMATION ........................................................................................................... 2
1.0 REGISTER MAP OF THE XRT74L74 ................................................................................................. 57
COMMONCONTROL REGISTERS OF THE XRT74L74...................................................................................................... 57
CLEAR-CHANNEL FRAMER BLOCK REGISTERS ................................................................................................. 58
RECEIVE ATM CELL PROCESSOR/PPP PROCESSOR BLOCK CONTROL REGISTERS .................................. 62
OPERATION BLOCK INTERRUPT REGISTER BIT FORMATS ................................................. 71
OPERATION CONTROL REGISTER - BYTE 3 (ADDRESS = 0X0100) ................................................................................. 71
OPERATION CONTROL REGISTER - BYTE 2 (ADDRESS = 0X0101) ................................................................................. 71
OPERATION CONTROL - LOOP-BACK CONTROL REGISTER (ADDRESS = 0X0102) ........................................................... 72
OPERATION CONTROL REGISTER - BYTE 0 (ADDRESS = 0X0103) ................................................................................. 73
DEVICE ID REGISTER (ADDRESS = 0X0104)................................................................................................................. 74
REVISION ID REGISTER (ADDRESS = 0X0105).............................................................................................................. 74
OPERATION INTERRUPT STATUS REGISTER - BYTE 1 (ADDRESS = 0X0112) .................................................................. 74
OPERATION INTERRUPT STATUS REGISTER - BYTE 0 (ADDRESS = 0X0113) .................................................................. 75
OPERATION INTERRUPT ENABLE REGISTER - BYTE 1 (ADDRESS = 0X0116) .................................................................. 76
OPERATION INTERRUPT ENABLE REGISTER - BYTE 0 (ADDRESS = 0X0117) .................................................................. 77
CHANNEL INTERRUPT INDICATION REGISTERS .................................................................... 78
CHANNEL INTERRUPT INDICATOR - RECEIVE CELL PROCESSOR/PPP PROCESSOR BLOCK (ADDRESS = 0X0119) ........... 79
CHANNEL INTERRUPT INDICATOR - LIU/JITTER ATTENUATOR BLOCK (ADDRESS = 0X011D) ........................................... 79
CHANNEL INTERRUPT INDICATOR - TRANSMIT CELL PROCESSOR/PPP PROCESSOR BLOCK (ADDRESS = 0X0121) ......... 80
CHANNEL INTERRUPT INDICATOR - DS3/E3 FRAMER BLOCK (ADDRESS = 0X0127) ....................................................... 80
OPERATION GENERAL PURPOSE PIN DATA REGISTER (ADDRESS = 0X0147)................................................................. 81
OPERATION GENERAL PURPOSE PIN DIRECTION CONTROL REGISTER (ADDRESS = 0X014B) ........................................ 81
RECEIVE UTOPIA INTERFACE BLOCK ..................................................................................... 82
TABLE 1: RECEIVE UTOPIA/POS-PHY INTERFACE BLOCK - REGISTER/ADDRESS MAP.......................................................................... 82
RECEIVE UTOPIA/POS-PHY CONTROL REGISTER - BYTE 0 (ADDRESS = 0X0503) ...................................................... 82
RECEIVE UTOPIA PORT ADDRESS REGISTER (ADDRESS = 0X0513) ............................................................................ 85
RECEIVE UTOPIA PORT NUMBER REGISTER (ADDRESS = 0X0517) ............................................................................. 85
TRANSMIT UTOPIA INTERFACE BLOCK .................................................................................. 87
TABLE 2: TRANSMIT UTOPIA INTERFACE BLOCK - REGISTER/ADDRESS MAP......................................................................................... 87
TRANSMIT UTOPIA/POS-PHY CONTROL REGISTER - BYTE 0 (ADDRESS = 0X0583) .................................................... 87
TRANSMIT UTOPIA PORT ADDRESS REGISTER (ADDRESS = 0X0593) .......................................................................... 90
TRANSMIT UTOPIA PORT NUMBER REGISTER (ADDRESS = 0X0597) ........................................................................... 90
2.0 MICROPROCESSOR INFO ................................................................................................................. 92
3.0 TRANSMIT SECTION .......................................................................................................................... 93
3.1 TRANSMIT UTOPIA INTERFACE BLOCK .................................................................................................... 93
3.1.1 BRIEF DESCRIPTION OF THE TRANSMIT UTOPIA INTERFACE........................................................................... 93
FIGURE 3. SIMPLE BLOCK DIAGRAM OF TRANSMIT UTOPIA INTERFACE................................................................................................. 94
3.1.2 FUNCTIONAL DESCRIPTION OF THE TRANSMIT UTOPIA INTERFACE .............................................................. 94
FIGURE 4. FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT UTOPIA BLOCK ........................................................................................ 95
FIGURE 5. TIMING DIAGRAM OF TXUCLAV/TXFULLB AND VARIOUS OTHER SIGNALS DURING WRITES TO THE TRANSMIT UTOPIA, WHILE OPER-
ATING IN THE OCTET-LEVEL HANDSHAKING MODE. ............................................................................................................... 100
FIGURE 6. TIMING DIAGRAM OF VARIOUS TRANSMIT UTOPIA INTERFACE BLOCK SIGNALS, WHEN THE TRANSMIT UTOPIA INTERFACE BLOCK IS
OPERATING IN THE “CELL LEVEL HANDSHAKING” MODE. ....................................................................................................... 101
FIGURE 7. SIMPLE ILLUSTRATION OF SINGLE-PHY OPERATION ............................................................................................................ 104
FIGURE 8. FLOW CHART DEPICTING THE APPROACH THAT THE ATM LAYER PROCESSOR SHOULD TAKE WHEN WRITING ATM CELL DATA INTO
THE TRANSMIT UTOPIA INTERFACE BLOCK, WHEN THE UNI IS OPERATING IN THE SINGLE PHY MODE.................................. 105
FIGURE 9. TIMING DIAGRAM OF ATM LAYER PROCESSOR TRANSMITTING DATA TO THE UNI OVER THE UTOPIA DATA BUS, (SINGLE -PHY
MODE/CELL-LEVEL HANDSHAKING)...................................................................................................................................... 106
FIGURE 10. TIMING DIAGRAM OF ATM LAYER PROCESSOR TRANSMITTING DATA TO THE UNI OVER THE UTOPIA DATA BUS (SINGLE-PHY
MODE/OCTET-LEVEL HANDSHAKING). .................................................................................................................................. 106
FIGURE 11. AN ILLUSTRATION OF MULTI-PHY OPERATION WITH UNI DEVICES #1 AND #2.................................................................... 108
FIGURE 12. TIMING DIAGRAM ILLUSTRATING THE BEHAVIOR OF VARIOUS SIGNALS FROM THE ATM LAYER PROCESSOR AND UNI, DURING POLL-
I